Jakob Stoklund Olesen 79c890f64f Add TargetRegisterInfo::getRawAllocationOrder(). ... This virtual function will replace allocation_order_begin/end as the one to override when implementing custom allocation orders. It is simpler to have one function return an ArrayRef than having two virtual functions computing different ends of the same array. Use getRawAllocationOrder() in place of allocation_order_begin() where it makes sense, but leave some clients that look like they really want the filtered allocation orders from RegisterClassInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133170 91177308-0d34-0410-b5e6-96231b3b80d8		2011-06-16 17:42:25 +00:00
..
CMakeLists.txt
DAGCombiner.cpp	Add a DAGCombine for (ext (binop (load x), cst)).	2011-06-16 01:15:49 +00:00
FastISel.cpp
FunctionLoweringInfo.cpp
InstrEmitter.cpp
InstrEmitter.h
LegalizeDAG.cpp
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp	getZeroExtendInReg needs to get a scalar type	2011-06-15 14:37:18 +00:00
LegalizeTypes.cpp
LegalizeTypes.h	Enable the simplification of truncating-store after fixing the usage of	2011-06-15 11:19:12 +00:00
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp	Add support for legalizing UINT_TO_FP of vectors on platforms which do	2011-03-19 13:09:10 +00:00
LegalizeVectorTypes.cpp
Makefile
ScheduleDAGFast.cpp
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp	Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.	2011-06-15 23:35:18 +00:00
ScheduleDAGSDNodes.cpp	Added -stress-sched flag in the Asserts build.	2011-06-15 17:16:12 +00:00
ScheduleDAGSDNodes.h	Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.	2011-06-15 23:35:18 +00:00
SDNodeDbgValue.h
SDNodeOrdering.h
SelectionDAG.cpp	Remove dead code.	2011-05-24 18:27:52 +00:00
SelectionDAGBuilder.cpp	Add TargetRegisterInfo::getRawAllocationOrder().	2011-06-16 17:42:25 +00:00
SelectionDAGBuilder.h
SelectionDAGISel.cpp
SelectionDAGPrinter.cpp
TargetLowering.cpp
TargetSelectionDAGInfo.cpp