..
CMakeLists.txt
Removed a bunch of unnecessary target_link_libraries.
2010-09-28 22:39:14 +00:00
DAGCombiner.cpp
Add a DAGCombine for (ext (binop (load x), cst)).
2011-06-16 01:15:49 +00:00
FastISel.cpp
PR10077: fix fast-isel of extractvalue of aggregate constants.
2011-06-06 05:46:34 +00:00
FunctionLoweringInfo.cpp
Add a parameter to CCState so that it can access the MachineFunction.
2011-06-08 23:55:35 +00:00
InstrEmitter.cpp
Use TRI::has{Sub,Super}ClassEq() where possible.
2011-06-02 05:43:46 +00:00
InstrEmitter.h
Don't set kill flags for instructions which the scheduler has cloned.
2010-05-14 22:01:14 +00:00
LegalizeDAG.cpp
Add a testcase for checking the integer-promotion of many different vector
2011-06-14 08:11:52 +00:00
LegalizeFloatTypes.cpp
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
2011-02-25 21:41:48 +00:00
LegalizeIntegerTypes.cpp
getZeroExtendInReg needs to get a scalar type
2011-06-15 14:37:18 +00:00
LegalizeTypes.cpp
Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use
2011-06-01 19:47:10 +00:00
LegalizeTypes.h
Enable the simplification of truncating-store after fixing the usage of
2011-06-15 11:19:12 +00:00
LegalizeTypesGeneric.cpp
Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use
2011-06-01 19:47:10 +00:00
LegalizeVectorOps.cpp
Add support for legalizing UINT_TO_FP of vectors on platforms which do
2011-03-19 13:09:10 +00:00
LegalizeVectorTypes.cpp
Fix a bug in FindMemType. When widening vector loads, use a wider memory type
2011-06-13 18:13:24 +00:00
Makefile
make -fno-rtti the default unless a directory builds with REQUIRES_RTTI.
2010-01-24 20:43:08 +00:00
ScheduleDAGFast.cpp
Re-commit 127368 and 127371. They are exonerated.
2011-03-10 00:16:32 +00:00
ScheduleDAGList.cpp
Various bits of framework needed for precise machine-level selection
2010-12-24 05:03:26 +00:00
ScheduleDAGRRList.cpp
Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.
2011-06-15 23:35:18 +00:00
ScheduleDAGSDNodes.cpp
Added -stress-sched flag in the Asserts build.
2011-06-15 17:16:12 +00:00
ScheduleDAGSDNodes.h
Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.
2011-06-15 23:35:18 +00:00
SDNodeDbgValue.h
Do not lose debug info of an inlined function argument even if the argument is only used through GEPs.
2011-02-18 22:43:42 +00:00
SDNodeOrdering.h
Allow 0 as an order number. Don't assign an order to formal arguments.
2009-12-22 21:35:02 +00:00
SelectionDAG.cpp
Remove dead code.
2011-05-24 18:27:52 +00:00
SelectionDAGBuilder.cpp
Add TargetRegisterInfo::getRawAllocationOrder().
2011-06-16 17:42:25 +00:00
SelectionDAGBuilder.h
Preserve debug info during iSel by keeping DanglingDebugInfoMap live until end of function.
2011-05-23 17:44:13 +00:00
SelectionDAGISel.cpp
Remove unused statistical counter.
2011-05-25 21:55:40 +00:00
SelectionDAGPrinter.cpp
Pass the graph to the DOTGraphTraits.getEdgeAttributes().
2011-02-27 04:11:03 +00:00
TargetLowering.cpp
Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd
2011-06-12 14:56:55 +00:00
TargetSelectionDAGInfo.cpp
Implement a bunch more TargetSelectionDAGInfo infrastructure.
2010-05-11 17:31:57 +00:00
79c890f64f