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https://github.com/c64scene-ar/llvm-6502.git
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c8c377d111
value types git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7377 91177308-0d34-0410-b5e6-96231b3b80d8
162 lines
5.4 KiB
C++
162 lines
5.4 KiB
C++
//===-- X86RegisterInfo.def - X86 Register Information ----------*- C++ -*-===//
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//
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// This file describes all of the registers that the X86 backend uses. It relies
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// on an external 'R' macro being defined that takes the arguments specified
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// below, and is used to make all of the information relevant to registers be in
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// one place.
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//
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//===----------------------------------------------------------------------===//
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// NOTE: No include guards desired
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#ifndef R
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#define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
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#endif
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#ifndef R8
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#define R8(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
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R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
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#endif
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#ifndef R16
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#define R16(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
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R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
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#endif
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#ifndef R32
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#define R32(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
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R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
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#endif
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// Pseudo Floating Point registers
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#ifndef PFP
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#define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
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R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
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#endif
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// Floating Point Stack registers
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#ifndef FPS
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#define FPS(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
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R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
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#endif
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// Arguments passed into the R macros
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// #1: Enum Name - This ends up being a symbol in the X86 namespace
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// #2: Register name - The name of the register as used by the gnu assembler
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// #3: Register Flags - A bitfield of flags or'd together from the
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// MRegisterInfo.h file.
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// #4: Target Specific Flags - Another bitfield containing X86 specific flags
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// as necessary.
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// #5: Alias set for registers aliased to this register (sets defined below).
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// The first register must always be a 'noop' register for all backends. This
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// is used as the destination register for instructions that do not produce a
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// value. Some frontends may use this as an operand register to mean special
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// things, for example, the Sparc backend uses R#0 to mean %g0 which always
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// PRODUCES the value 0.
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//
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// The X86 backend uses this value as an operand register only in memory
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// references where it means that there is no base or index register.
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//
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R(NoReg,"none", 0, 0, 0/*noalias*/)
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// 32 bit registers, ordered as the processor does...
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R32(EAX, "EAX", MVT::i32, 0, A_EAX)
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R32(ECX, "ECX", MVT::i32, 0, A_ECX)
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R32(EDX, "EDX", MVT::i32, 0, A_EDX)
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R32(EBX, "EBX", MVT::i32, 0, A_EBX)
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R32(ESP, "ESP", MVT::i32, 0, A_ESP)
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R32(EBP, "EBP", MVT::i32, 0, A_EBP)
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R32(ESI, "ESI", MVT::i32, 0, A_ESI)
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R32(EDI, "EDI", MVT::i32, 0, A_EDI)
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// 16 bit registers, aliased with the corresponding 32 bit registers above
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R16( AX, "AX" , MVT::i16, 0, A_AX)
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R16( CX, "CX" , MVT::i16, 0, A_CX)
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R16( DX, "DX" , MVT::i16, 0, A_DX)
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R16( BX, "BX" , MVT::i16, 0, A_BX)
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R16( SP, "SP" , MVT::i16, 0, A_SP)
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R16( BP, "BP" , MVT::i16, 0, A_BP)
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R16( SI, "SI" , MVT::i16, 0, A_SI)
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R16( DI, "DI" , MVT::i16, 0, A_DI)
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// 8 bit registers aliased with registers above as well
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R8 ( AL, "AL" , MVT::i8 , 0, A_AL)
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R8 ( CL, "CL" , MVT::i8 , 0, A_CL)
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R8 ( DL, "DL" , MVT::i8 , 0, A_DL)
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R8 ( BL, "BL" , MVT::i8 , 0, A_BL)
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R8 ( AH, "AH" , MVT::i8 , 0, A_AH)
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R8 ( CH, "CH" , MVT::i8 , 0, A_CH)
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R8 ( DH, "DH" , MVT::i8 , 0, A_DH)
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R8 ( BH, "BH" , MVT::i8 , 0, A_BH)
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// Pseudo Floating Point Registers
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PFP(FP0, "FP0", MVT::f80 , 0, 0 /*noalias*/)
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PFP(FP1, "FP1", MVT::f80 , 0, 0 /*noalias*/)
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PFP(FP2, "FP2", MVT::f80 , 0, 0 /*noalias*/)
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PFP(FP3, "FP3", MVT::f80 , 0, 0 /*noalias*/)
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PFP(FP4, "FP4", MVT::f80 , 0, 0 /*noalias*/)
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PFP(FP5, "FP5", MVT::f80 , 0, 0 /*noalias*/)
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PFP(FP6, "FP6", MVT::f80 , 0, 0 /*noalias*/)
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// Floating point stack registers
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FPS(ST0, "ST(0)", MVT::f80, 0, 0)
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FPS(ST1, "ST(1)", MVT::f80, 0, 0)
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FPS(ST2, "ST(2)", MVT::f80, 0, 0)
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FPS(ST3, "ST(3)", MVT::f80, 0, 0)
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FPS(ST4, "ST(4)", MVT::f80, 0, 0)
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FPS(ST5, "ST(5)", MVT::f80, 0, 0)
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FPS(ST6, "ST(6)", MVT::f80, 0, 0)
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FPS(ST7, "ST(7)", MVT::f80, 0, 0)
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// Flags, Segment registers, etc...
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// This is a slimy hack to make it possible to say that flags are clobbered...
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// Ideally we'd model instructions based on which particular flag(s) they
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// could clobber.
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R(EFLAGS, "EFLAGS", MVT::i16, 0, 0 /*noalias*/)
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//===----------------------------------------------------------------------===//
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// Register alias set handling...
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//
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// Macro to handle definitions of alias sets that registers use...
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#ifndef ALIASLIST
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#define ALIASLIST(NAME, ...)
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#endif
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ALIASLIST(A_EAX , X86::AX, X86::AH, X86::AL, 0)
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ALIASLIST(A_ECX , X86::CX, X86::CH, X86::CL, 0)
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ALIASLIST(A_EDX , X86::DX, X86::DH, X86::DL, 0)
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ALIASLIST(A_EBX , X86::BX, X86::BH, X86::BL, 0)
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ALIASLIST(A_ESP , X86::SP, 0)
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ALIASLIST(A_EBP , X86::BP, 0)
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ALIASLIST(A_ESI , X86::SI, 0)
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ALIASLIST(A_EDI , X86::DI, 0)
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ALIASLIST(A_AX , X86::EAX, X86::AH, X86::AL, 0)
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ALIASLIST(A_CX , X86::ECX, X86::CH, X86::CL, 0)
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ALIASLIST(A_DX , X86::EDX, X86::DH, X86::DL, 0)
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ALIASLIST(A_BX , X86::EBX, X86::BH, X86::BL, 0)
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ALIASLIST(A_SP , X86::ESP, 0)
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ALIASLIST(A_BP , X86::EBP, 0)
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ALIASLIST(A_SI , X86::ESI, 0)
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ALIASLIST(A_DI , X86::EDI, 0)
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ALIASLIST(A_AL , X86::EAX, X86::AX, 0)
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ALIASLIST(A_CL , X86::ECX, X86::CX, 0)
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ALIASLIST(A_DL , X86::EDX, X86::DX, 0)
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ALIASLIST(A_BL , X86::EBX, X86::BX, 0)
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ALIASLIST(A_AH , X86::EAX, X86::AX, 0)
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ALIASLIST(A_CH , X86::ECX, X86::CX, 0)
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ALIASLIST(A_DH , X86::EDX, X86::DX, 0)
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ALIASLIST(A_BH , X86::EBX, X86::BX, 0)
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#undef ALIASLIST
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// We are now done with the R* macros
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#undef R
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#undef R8
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#undef R16
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#undef R32
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#undef PFP
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#undef FPS
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