mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-30 17:33:24 +00:00
fadbf53e7e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207753 91177308-0d34-0410-b5e6-96231b3b80d8
4202 lines
115 KiB
Plaintext
4202 lines
115 KiB
Plaintext
# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s
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#------------------------------------------------------------------------------
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# Add/sub (immediate)
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#------------------------------------------------------------------------------
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# CHECK: add w4, w5, #0
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# CHECK: add w2, w3, #4095
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# CHECK: add w30, w29, #1, lsl #12
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# CHECK: add w13, w5, #4095, lsl #12
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# CHECK: add x5, x7, #1638
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0xa4 0x0 0x0 0x11
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0x62 0xfc 0x3f 0x11
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0xbe 0x7 0x40 0x11
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0xad 0xfc 0x7f 0x11
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0xe5 0x98 0x19 0x91
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# CHECK: add w20, wsp, #801
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# CHECK: add wsp, wsp, #1104
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# CHECK: add wsp, w30, #4084
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0xf4 0x87 0xc 0x11
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0xff 0x43 0x11 0x11
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0xdf 0xd3 0x3f 0x11
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# CHECK: add x0, x24, #291
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# CHECK: add x3, x24, #4095, lsl #12
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# CHECK: add x8, sp, #1074
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# CHECK: add sp, x29, #3816
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0x0 0x8f 0x4 0x91
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0x3 0xff 0x7f 0x91
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0xe8 0xcb 0x10 0x91
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0xbf 0xa3 0x3b 0x91
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# CHECK: sub w0, wsp, #4077
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# CHECK: sub w4, w20, #546, lsl #12
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# CHECK: sub sp, sp, #288
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# CHECK: sub wsp, w19, #16
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0xe0 0xb7 0x3f 0x51
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0x84 0x8a 0x48 0x51
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0xff 0x83 0x4 0xd1
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0x7f 0x42 0x0 0x51
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# CHECK: adds w13, w23, #291, lsl #12
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# CHECK: cmn w2, #4095
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# CHECK: adds w20, wsp, #0
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# CHECK: cmn x3, #1, lsl #12
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0xed 0x8e 0x44 0x31
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0x5f 0xfc 0x3f 0x31
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0xf4 0x3 0x0 0x31
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0x7f 0x4 0x40 0xb1
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# CHECK: cmp sp, #20, lsl #12
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# CHECK: cmp x30, #4095
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# CHECK: subs x4, sp, #3822
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0xff 0x53 0x40 0xf1
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0xdf 0xff 0x3f 0xf1
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0xe4 0xbb 0x3b 0xf1
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# These should really be CMN
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# CHECK: cmn w3, #291, lsl #12
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# CHECK: cmn wsp, #1365
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# CHECK: cmn sp, #1092, lsl #12
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0x7f 0x8c 0x44 0x31
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0xff 0x57 0x15 0x31
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0xff 0x13 0x51 0xb1
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# CHECK: mov sp, x30
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# CHECK: mov wsp, w20
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# CHECK: mov x11, sp
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# CHECK: mov w24, wsp
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0xdf 0x3 0x0 0x91
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0x9f 0x2 0x0 0x11
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0xeb 0x3 0x0 0x91
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0xf8 0x3 0x0 0x11
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#------------------------------------------------------------------------------
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# Add-subtract (shifted register)
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#------------------------------------------------------------------------------
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# CHECK: add w3, w5, w7
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# CHECK: add wzr, w3, w5
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# CHECK: add w20, wzr, w4
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# CHECK: add w4, w6, wzr
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# CHECK: add w11, w13, w15
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# CHECK: add w9, w3, wzr, lsl #10
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# CHECK: add w17, w29, w20, lsl #31
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# CHECK: add w21, w22, w23, lsr #0
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# CHECK: add w24, w25, w26, lsr #18
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# CHECK: add w27, w28, w29, lsr #31
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# CHECK: add w2, w3, w4, asr #0
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# CHECK: add w5, w6, w7, asr #21
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# CHECK: add w8, w9, w10, asr #31
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0xa3 0x0 0x7 0xb
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0x7f 0x0 0x5 0xb
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0xf4 0x3 0x4 0xb
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0xc4 0x0 0x1f 0xb
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0xab 0x1 0xf 0xb
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0x69 0x28 0x1f 0xb
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0xb1 0x7f 0x14 0xb
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0xd5 0x2 0x57 0xb
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0x38 0x4b 0x5a 0xb
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0x9b 0x7f 0x5d 0xb
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0x62 0x0 0x84 0xb
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0xc5 0x54 0x87 0xb
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0x28 0x7d 0x8a 0xb
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# CHECK: add x3, x5, x7
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# CHECK: add xzr, x3, x5
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# CHECK: add x20, xzr, x4
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# CHECK: add x4, x6, xzr
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# CHECK: add x11, x13, x15
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# CHECK: add x9, x3, xzr, lsl #10
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# CHECK: add x17, x29, x20, lsl #63
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# CHECK: add x21, x22, x23, lsr #0
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# CHECK: add x24, x25, x26, lsr #18
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# CHECK: add x27, x28, x29, lsr #63
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# CHECK: add x2, x3, x4, asr #0
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# CHECK: add x5, x6, x7, asr #21
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# CHECK: add x8, x9, x10, asr #63
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0xa3 0x0 0x7 0x8b
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0x7f 0x0 0x5 0x8b
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0xf4 0x3 0x4 0x8b
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0xc4 0x0 0x1f 0x8b
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0xab 0x1 0xf 0x8b
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0x69 0x28 0x1f 0x8b
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0xb1 0xff 0x14 0x8b
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0xd5 0x2 0x57 0x8b
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0x38 0x4b 0x5a 0x8b
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0x9b 0xff 0x5d 0x8b
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0x62 0x0 0x84 0x8b
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0xc5 0x54 0x87 0x8b
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0x28 0xfd 0x8a 0x8b
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# CHECK: adds w3, w5, w7
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# CHECK: cmn w3, w5
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# CHECK: adds w20, wzr, w4
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# CHECK: adds w4, w6, wzr
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# CHECK: adds w11, w13, w15
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# CHECK: adds w9, w3, wzr, lsl #10
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# CHECK: adds w17, w29, w20, lsl #31
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# CHECK: adds w21, w22, w23, lsr #0
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# CHECK: adds w24, w25, w26, lsr #18
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# CHECK: adds w27, w28, w29, lsr #31
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# CHECK: adds w2, w3, w4, asr #0
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# CHECK: adds w5, w6, w7, asr #21
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# CHECK: adds w8, w9, w10, asr #31
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0xa3 0x0 0x7 0x2b
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0x7f 0x0 0x5 0x2b
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0xf4 0x3 0x4 0x2b
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0xc4 0x0 0x1f 0x2b
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0xab 0x1 0xf 0x2b
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0x69 0x28 0x1f 0x2b
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0xb1 0x7f 0x14 0x2b
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0xd5 0x2 0x57 0x2b
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0x38 0x4b 0x5a 0x2b
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0x9b 0x7f 0x5d 0x2b
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0x62 0x0 0x84 0x2b
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0xc5 0x54 0x87 0x2b
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0x28 0x7d 0x8a 0x2b
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# CHECK: adds x3, x5, x7
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# CHECK: cmn x3, x5
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# CHECK: adds x20, xzr, x4
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# CHECK: adds x4, x6, xzr
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# CHECK: adds x11, x13, x15
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# CHECK: adds x9, x3, xzr, lsl #10
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# CHECK: adds x17, x29, x20, lsl #63
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# CHECK: adds x21, x22, x23, lsr #0
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# CHECK: adds x24, x25, x26, lsr #18
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# CHECK: adds x27, x28, x29, lsr #63
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# CHECK: adds x2, x3, x4, asr #0
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# CHECK: adds x5, x6, x7, asr #21
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# CHECK: adds x8, x9, x10, asr #63
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0xa3 0x0 0x7 0xab
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0x7f 0x0 0x5 0xab
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0xf4 0x3 0x4 0xab
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0xc4 0x0 0x1f 0xab
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0xab 0x1 0xf 0xab
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0x69 0x28 0x1f 0xab
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0xb1 0xff 0x14 0xab
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0xd5 0x2 0x57 0xab
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0x38 0x4b 0x5a 0xab
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0x9b 0xff 0x5d 0xab
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0x62 0x0 0x84 0xab
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0xc5 0x54 0x87 0xab
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0x28 0xfd 0x8a 0xab
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# CHECK: sub w3, w5, w7
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# CHECK: sub wzr, w3, w5
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# CHECK: {{sub w20, wzr, w4|neg w20, w4}}
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# CHECK: sub w4, w6, wzr
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# CHECK: sub w11, w13, w15
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# CHECK: sub w9, w3, wzr, lsl #10
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# CHECK: sub w17, w29, w20, lsl #31
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# CHECK: sub w21, w22, w23, lsr #0
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# CHECK: sub w24, w25, w26, lsr #18
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# CHECK: sub w27, w28, w29, lsr #31
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# CHECK: sub w2, w3, w4, asr #0
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# CHECK: sub w5, w6, w7, asr #21
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# CHECK: sub w8, w9, w10, asr #31
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0xa3 0x0 0x7 0x4b
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0x7f 0x0 0x5 0x4b
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0xf4 0x3 0x4 0x4b
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0xc4 0x0 0x1f 0x4b
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0xab 0x1 0xf 0x4b
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0x69 0x28 0x1f 0x4b
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0xb1 0x7f 0x14 0x4b
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0xd5 0x2 0x57 0x4b
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0x38 0x4b 0x5a 0x4b
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0x9b 0x7f 0x5d 0x4b
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0x62 0x0 0x84 0x4b
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0xc5 0x54 0x87 0x4b
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0x28 0x7d 0x8a 0x4b
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# CHECK: sub x3, x5, x7
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# CHECK: sub xzr, x3, x5
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# CHECK: {{sub x20, xzr, x4|neg x20, x4}}
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# CHECK: sub x4, x6, xzr
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# CHECK: sub x11, x13, x15
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# CHECK: sub x9, x3, xzr, lsl #10
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# CHECK: sub x17, x29, x20, lsl #63
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# CHECK: sub x21, x22, x23, lsr #0
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# CHECK: sub x24, x25, x26, lsr #18
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# CHECK: sub x27, x28, x29, lsr #63
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# CHECK: sub x2, x3, x4, asr #0
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# CHECK: sub x5, x6, x7, asr #21
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# CHECK: sub x8, x9, x10, asr #63
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0xa3 0x0 0x7 0xcb
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0x7f 0x0 0x5 0xcb
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0xf4 0x3 0x4 0xcb
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0xc4 0x0 0x1f 0xcb
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0xab 0x1 0xf 0xcb
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0x69 0x28 0x1f 0xcb
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0xb1 0xff 0x14 0xcb
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0xd5 0x2 0x57 0xcb
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0x38 0x4b 0x5a 0xcb
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0x9b 0xff 0x5d 0xcb
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0x62 0x0 0x84 0xcb
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0xc5 0x54 0x87 0xcb
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0x28 0xfd 0x8a 0xcb
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# CHECK: subs w3, w5, w7
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# CHECK: cmp w3, w5
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# CHECK: {{subs w20, wzr, w4|negs w20, w4}}
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# CHECK: subs w4, w6, wzr
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# CHECK: subs w11, w13, w15
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# CHECK: subs w9, w3, wzr, lsl #10
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# CHECK: subs w17, w29, w20, lsl #31
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# CHECK: subs w21, w22, w23, lsr #0
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# CHECK: subs w24, w25, w26, lsr #18
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# CHECK: subs w27, w28, w29, lsr #31
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# CHECK: subs w2, w3, w4, asr #0
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# CHECK: subs w5, w6, w7, asr #21
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# CHECK: subs w8, w9, w10, asr #31
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0xa3 0x0 0x7 0x6b
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0x7f 0x0 0x5 0x6b
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0xf4 0x3 0x4 0x6b
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0xc4 0x0 0x1f 0x6b
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0xab 0x1 0xf 0x6b
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0x69 0x28 0x1f 0x6b
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0xb1 0x7f 0x14 0x6b
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0xd5 0x2 0x57 0x6b
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0x38 0x4b 0x5a 0x6b
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0x9b 0x7f 0x5d 0x6b
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0x62 0x0 0x84 0x6b
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0xc5 0x54 0x87 0x6b
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0x28 0x7d 0x8a 0x6b
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# CHECK: subs x3, x5, x7
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# CHECK: cmp x3, x5
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# CHECK: {{subs x20, xzr, x4|negs x20, x4}}
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# CHECK: subs x4, x6, xzr
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# CHECK: subs x11, x13, x15
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# CHECK: subs x9, x3, xzr, lsl #10
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# CHECK: subs x17, x29, x20, lsl #63
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# CHECK: subs x21, x22, x23, lsr #0
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# CHECK: subs x24, x25, x26, lsr #18
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# CHECK: subs x27, x28, x29, lsr #63
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# CHECK: subs x2, x3, x4, asr #0
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# CHECK: subs x5, x6, x7, asr #21
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# CHECK: subs x8, x9, x10, asr #63
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0xa3 0x0 0x7 0xeb
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0x7f 0x0 0x5 0xeb
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0xf4 0x3 0x4 0xeb
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0xc4 0x0 0x1f 0xeb
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0xab 0x1 0xf 0xeb
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0x69 0x28 0x1f 0xeb
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0xb1 0xff 0x14 0xeb
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0xd5 0x2 0x57 0xeb
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0x38 0x4b 0x5a 0xeb
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0x9b 0xff 0x5d 0xeb
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0x62 0x0 0x84 0xeb
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0xc5 0x54 0x87 0xeb
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0x28 0xfd 0x8a 0xeb
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# CHECK: cmn w0, w3
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# CHECK: cmn wzr, w4
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# CHECK: cmn w5, wzr
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# CHECK: cmn w6, w7
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# CHECK: cmn w8, w9, lsl #15
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# CHECK: cmn w10, w11, lsl #31
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# CHECK: cmn w12, w13, lsr #0
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# CHECK: cmn w14, w15, lsr #21
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# CHECK: cmn w16, w17, lsr #31
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# CHECK: cmn w18, w19, asr #0
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# CHECK: cmn w20, w21, asr #22
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# CHECK: cmn w22, w23, asr #31
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0x1f 0x0 0x3 0x2b
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0xff 0x3 0x4 0x2b
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0xbf 0x0 0x1f 0x2b
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0xdf 0x0 0x7 0x2b
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0x1f 0x3d 0x9 0x2b
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0x5f 0x7d 0xb 0x2b
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0x9f 0x1 0x4d 0x2b
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0xdf 0x55 0x4f 0x2b
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0x1f 0x7e 0x51 0x2b
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0x5f 0x2 0x93 0x2b
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0x9f 0x5a 0x95 0x2b
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0xdf 0x7e 0x97 0x2b
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# CHECK: cmn x0, x3
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# CHECK: cmn xzr, x4
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# CHECK: cmn x5, xzr
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# CHECK: cmn x6, x7
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# CHECK: cmn x8, x9, lsl #15
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# CHECK: cmn x10, x11, lsl #63
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# CHECK: cmn x12, x13, lsr #0
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# CHECK: cmn x14, x15, lsr #41
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# CHECK: cmn x16, x17, lsr #63
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# CHECK: cmn x18, x19, asr #0
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# CHECK: cmn x20, x21, asr #55
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# CHECK: cmn x22, x23, asr #63
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0x1f 0x0 0x3 0xab
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0xff 0x3 0x4 0xab
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0xbf 0x0 0x1f 0xab
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0xdf 0x0 0x7 0xab
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0x1f 0x3d 0x9 0xab
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0x5f 0xfd 0xb 0xab
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0x9f 0x1 0x4d 0xab
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0xdf 0xa5 0x4f 0xab
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0x1f 0xfe 0x51 0xab
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0x5f 0x2 0x93 0xab
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0x9f 0xde 0x95 0xab
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0xdf 0xfe 0x97 0xab
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# CHECK: cmp w0, w3
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# CHECK: cmp wzr, w4
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# CHECK: cmp w5, wzr
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# CHECK: cmp w6, w7
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# CHECK: cmp w8, w9, lsl #15
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# CHECK: cmp w10, w11, lsl #31
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# CHECK: cmp w12, w13, lsr #0
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# CHECK: cmp w14, w15, lsr #21
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# CHECK: cmp w16, w17, lsr #31
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# CHECK: cmp w18, w19, asr #0
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# CHECK: cmp w20, w21, asr #22
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# CHECK: cmp w22, w23, asr #31
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0x1f 0x0 0x3 0x6b
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0xff 0x3 0x4 0x6b
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0xbf 0x0 0x1f 0x6b
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0xdf 0x0 0x7 0x6b
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0x1f 0x3d 0x9 0x6b
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0x5f 0x7d 0xb 0x6b
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0x9f 0x1 0x4d 0x6b
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0xdf 0x55 0x4f 0x6b
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0x1f 0x7e 0x51 0x6b
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0x5f 0x2 0x93 0x6b
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0x9f 0x5a 0x95 0x6b
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0xdf 0x7e 0x97 0x6b
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# CHECK: cmp x0, x3
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# CHECK: cmp xzr, x4
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# CHECK: cmp x5, xzr
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# CHECK: cmp x6, x7
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# CHECK: cmp x8, x9, lsl #15
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# CHECK: cmp x10, x11, lsl #63
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# CHECK: cmp x12, x13, lsr #0
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# CHECK: cmp x14, x15, lsr #41
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# CHECK: cmp x16, x17, lsr #63
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# CHECK: cmp x18, x19, asr #0
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# CHECK: cmp x20, x21, asr #55
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# CHECK: cmp x22, x23, asr #63
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0x1f 0x0 0x3 0xeb
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0xff 0x3 0x4 0xeb
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0xbf 0x0 0x1f 0xeb
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0xdf 0x0 0x7 0xeb
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0x1f 0x3d 0x9 0xeb
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0x5f 0xfd 0xb 0xeb
|
|
0x9f 0x1 0x4d 0xeb
|
|
0xdf 0xa5 0x4f 0xeb
|
|
0x1f 0xfe 0x51 0xeb
|
|
0x5f 0x2 0x93 0xeb
|
|
0x9f 0xde 0x95 0xeb
|
|
0xdf 0xfe 0x97 0xeb
|
|
|
|
# CHECK: {{sub w29, wzr|neg w29}}, w30
|
|
# CHECK: {{sub w30, wzr|neg w30}}, wzr
|
|
# CHECK: {{sub wzr, wzr|neg wzr}}, w0
|
|
# CHECK: {{sub w28, wzr|neg w28}}, w27
|
|
# CHECK: {{sub w26, wzr|neg w26}}, w25, lsl #29
|
|
# CHECK: {{sub w24, wzr|neg w24}}, w23, lsl #31
|
|
# CHECK: {{sub w22, wzr|neg w22}}, w21, lsr #0
|
|
# CHECK: {{sub w20, wzr|neg w20}}, w19, lsr #1
|
|
# CHECK: {{sub w18, wzr|neg w18}}, w17, lsr #31
|
|
# CHECK: {{sub w16, wzr|neg w16}}, w15, asr #0
|
|
# CHECK: {{sub w14, wzr|neg w14}}, w13, asr #12
|
|
# CHECK: {{sub w12, wzr|neg w12}}, w11, asr #31
|
|
0xfd 0x3 0x1e 0x4b
|
|
0xfe 0x3 0x1f 0x4b
|
|
0xff 0x3 0x0 0x4b
|
|
0xfc 0x3 0x1b 0x4b
|
|
0xfa 0x77 0x19 0x4b
|
|
0xf8 0x7f 0x17 0x4b
|
|
0xf6 0x3 0x55 0x4b
|
|
0xf4 0x7 0x53 0x4b
|
|
0xf2 0x7f 0x51 0x4b
|
|
0xf0 0x3 0x8f 0x4b
|
|
0xee 0x33 0x8d 0x4b
|
|
0xec 0x7f 0x8b 0x4b
|
|
|
|
# CHECK: {{sub x29, xzr|neg x29}}, x30
|
|
# CHECK: {{sub x30, xzr|neg x30}}, xzr
|
|
# CHECK: {{sub xzr, xzr|neg xzr}}, x0
|
|
# CHECK: {{sub x28, xzr|neg x28}}, x27
|
|
# CHECK: {{sub x26, xzr|neg x26}}, x25, lsl #29
|
|
# CHECK: {{sub x24, xzr|neg x24}}, x23, lsl #31
|
|
# CHECK: {{sub x22, xzr|neg x22}}, x21, lsr #0
|
|
# CHECK: {{sub x20, xzr|neg x20}}, x19, lsr #1
|
|
# CHECK: {{sub x18, xzr|neg x18}}, x17, lsr #31
|
|
# CHECK: {{sub x16, xzr|neg x16}}, x15, asr #0
|
|
# CHECK: {{sub x14, xzr|neg x14}}, x13, asr #12
|
|
# CHECK: {{sub x12, xzr|neg x12}}, x11, asr #31
|
|
0xfd 0x3 0x1e 0xcb
|
|
0xfe 0x3 0x1f 0xcb
|
|
0xff 0x3 0x0 0xcb
|
|
0xfc 0x3 0x1b 0xcb
|
|
0xfa 0x77 0x19 0xcb
|
|
0xf8 0x7f 0x17 0xcb
|
|
0xf6 0x3 0x55 0xcb
|
|
0xf4 0x7 0x53 0xcb
|
|
0xf2 0x7f 0x51 0xcb
|
|
0xf0 0x3 0x8f 0xcb
|
|
0xee 0x33 0x8d 0xcb
|
|
0xec 0x7f 0x8b 0xcb
|
|
|
|
# CHECK: {{subs w29, wzr|negs w29}}, w30
|
|
# CHECK: {{subs w30, wzr|negs w30}}, wzr
|
|
# CHECK: cmp wzr, w0
|
|
# CHECK: {{subs w28, wzr|negs w28}}, w27
|
|
# CHECK: {{subs w26, wzr|negs w26}}, w25, lsl #29
|
|
# CHECK: {{subs w24, wzr|negs w24}}, w23, lsl #31
|
|
# CHECK: {{subs w22, wzr|negs w22}}, w21, lsr #0
|
|
# CHECK: {{subs w20, wzr|negs w20}}, w19, lsr #1
|
|
# CHECK: {{subs w18, wzr|negs w18}}, w17, lsr #31
|
|
# CHECK: {{subs w16, wzr|negs w16}}, w15, asr #0
|
|
# CHECK: {{subs w14, wzr|negs w14}}, w13, asr #12
|
|
# CHECK: {{subs w12, wzr|negs w12}}, w11, asr #31
|
|
0xfd 0x3 0x1e 0x6b
|
|
0xfe 0x3 0x1f 0x6b
|
|
0xff 0x3 0x0 0x6b
|
|
0xfc 0x3 0x1b 0x6b
|
|
0xfa 0x77 0x19 0x6b
|
|
0xf8 0x7f 0x17 0x6b
|
|
0xf6 0x3 0x55 0x6b
|
|
0xf4 0x7 0x53 0x6b
|
|
0xf2 0x7f 0x51 0x6b
|
|
0xf0 0x3 0x8f 0x6b
|
|
0xee 0x33 0x8d 0x6b
|
|
0xec 0x7f 0x8b 0x6b
|
|
|
|
# CHECK: {{subs x29, xzr|negs x29}}, x30
|
|
# CHECK: {{subs x30, xzr|negs x30}}, xzr
|
|
# CHECK: cmp xzr, x0
|
|
# CHECK: {{subs x28, xzr|negs x28}}, x27
|
|
# CHECK: {{subs x26, xzr|negs x26}}, x25, lsl #29
|
|
# CHECK: {{subs x24, xzr|negs x24}}, x23, lsl #31
|
|
# CHECK: {{subs x22, xzr|negs x22}}, x21, lsr #0
|
|
# CHECK: {{subs x20, xzr|negs x20}}, x19, lsr #1
|
|
# CHECK: {{subs x18, xzr|negs x18}}, x17, lsr #31
|
|
# CHECK: {{subs x16, xzr|negs x16}}, x15, asr #0
|
|
# CHECK: {{subs x14, xzr|negs x14}}, x13, asr #12
|
|
# CHECK: {{subs x12, xzr|negs x12}}, x11, asr #31
|
|
0xfd 0x3 0x1e 0xeb
|
|
0xfe 0x3 0x1f 0xeb
|
|
0xff 0x3 0x0 0xeb
|
|
0xfc 0x3 0x1b 0xeb
|
|
0xfa 0x77 0x19 0xeb
|
|
0xf8 0x7f 0x17 0xeb
|
|
0xf6 0x3 0x55 0xeb
|
|
0xf4 0x7 0x53 0xeb
|
|
0xf2 0x7f 0x51 0xeb
|
|
0xf0 0x3 0x8f 0xeb
|
|
0xee 0x33 0x8d 0xeb
|
|
0xec 0x7f 0x8b 0xeb
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Add-subtract (shifted register)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: adc w29, w27, w25
|
|
# CHECK: adc wzr, w3, w4
|
|
# CHECK: adc w9, wzr, w10
|
|
# CHECK: adc w20, w0, wzr
|
|
0x7d 0x3 0x19 0x1a
|
|
0x7f 0x0 0x4 0x1a
|
|
0xe9 0x3 0xa 0x1a
|
|
0x14 0x0 0x1f 0x1a
|
|
|
|
# CHECK: adc x29, x27, x25
|
|
# CHECK: adc xzr, x3, x4
|
|
# CHECK: adc x9, xzr, x10
|
|
# CHECK: adc x20, x0, xzr
|
|
0x7d 0x3 0x19 0x9a
|
|
0x7f 0x0 0x4 0x9a
|
|
0xe9 0x3 0xa 0x9a
|
|
0x14 0x0 0x1f 0x9a
|
|
|
|
# CHECK: adcs w29, w27, w25
|
|
# CHECK: adcs wzr, w3, w4
|
|
# CHECK: adcs w9, wzr, w10
|
|
# CHECK: adcs w20, w0, wzr
|
|
0x7d 0x3 0x19 0x3a
|
|
0x7f 0x0 0x4 0x3a
|
|
0xe9 0x3 0xa 0x3a
|
|
0x14 0x0 0x1f 0x3a
|
|
|
|
# CHECK: adcs x29, x27, x25
|
|
# CHECK: adcs xzr, x3, x4
|
|
# CHECK: adcs x9, xzr, x10
|
|
# CHECK: adcs x20, x0, xzr
|
|
0x7d 0x3 0x19 0xba
|
|
0x7f 0x0 0x4 0xba
|
|
0xe9 0x3 0xa 0xba
|
|
0x14 0x0 0x1f 0xba
|
|
|
|
# CHECK: sbc w29, w27, w25
|
|
# CHECK: sbc wzr, w3, w4
|
|
# CHECK: ngc w9, w10
|
|
# CHECK: sbc w20, w0, wzr
|
|
0x7d 0x3 0x19 0x5a
|
|
0x7f 0x0 0x4 0x5a
|
|
0xe9 0x3 0xa 0x5a
|
|
0x14 0x0 0x1f 0x5a
|
|
|
|
# CHECK: sbc x29, x27, x25
|
|
# CHECK: sbc xzr, x3, x4
|
|
# CHECK: ngc x9, x10
|
|
# CHECK: sbc x20, x0, xzr
|
|
0x7d 0x3 0x19 0xda
|
|
0x7f 0x0 0x4 0xda
|
|
0xe9 0x3 0xa 0xda
|
|
0x14 0x0 0x1f 0xda
|
|
|
|
# CHECK: sbcs w29, w27, w25
|
|
# CHECK: sbcs wzr, w3, w4
|
|
# CHECK: ngcs w9, w10
|
|
# CHECK: sbcs w20, w0, wzr
|
|
0x7d 0x3 0x19 0x7a
|
|
0x7f 0x0 0x4 0x7a
|
|
0xe9 0x3 0xa 0x7a
|
|
0x14 0x0 0x1f 0x7a
|
|
|
|
# CHECK: sbcs x29, x27, x25
|
|
# CHECK: sbcs xzr, x3, x4
|
|
# CHECK: ngcs x9, x10
|
|
# CHECK: sbcs x20, x0, xzr
|
|
0x7d 0x3 0x19 0xfa
|
|
0x7f 0x0 0x4 0xfa
|
|
0xe9 0x3 0xa 0xfa
|
|
0x14 0x0 0x1f 0xfa
|
|
|
|
# CHECK: ngc w3, w12
|
|
# CHECK: ngc wzr, w9
|
|
# CHECK: ngc w23, wzr
|
|
0xe3 0x3 0xc 0x5a
|
|
0xff 0x3 0x9 0x5a
|
|
0xf7 0x3 0x1f 0x5a
|
|
|
|
# CHECK: ngc x29, x30
|
|
# CHECK: ngc xzr, x0
|
|
# CHECK: ngc x0, xzr
|
|
0xfd 0x3 0x1e 0xda
|
|
0xff 0x3 0x0 0xda
|
|
0xe0 0x3 0x1f 0xda
|
|
|
|
# CHECK: ngcs w3, w12
|
|
# CHECK: ngcs wzr, w9
|
|
# CHECK: ngcs w23, wzr
|
|
0xe3 0x3 0xc 0x7a
|
|
0xff 0x3 0x9 0x7a
|
|
0xf7 0x3 0x1f 0x7a
|
|
|
|
# CHECK: ngcs x29, x30
|
|
# CHECK: ngcs xzr, x0
|
|
# CHECK: ngcs x0, xzr
|
|
0xfd 0x3 0x1e 0xfa
|
|
0xff 0x3 0x0 0xfa
|
|
0xe0 0x3 0x1f 0xfa
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Compare and branch (immediate)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: sbfx x1, x2, #3, #2
|
|
# CHECK: asr x3, x4, #63
|
|
# CHECK: asr wzr, wzr, #31
|
|
# CHECK: sbfx w12, w9, #0, #1
|
|
0x41 0x10 0x43 0x93
|
|
0x83 0xfc 0x7f 0x93
|
|
0xff 0x7f 0x1f 0x13
|
|
0x2c 0x1 0x0 0x13
|
|
|
|
# CHECK: ubfiz x4, x5, #52, #11
|
|
# CHECK: ubfx xzr, x4, #0, #1
|
|
# CHECK: ubfiz x4, xzr, #1, #6
|
|
# CHECK: lsr x5, x6, #12
|
|
0xa4 0x28 0x4c 0xd3
|
|
0x9f 0x0 0x40 0xd3
|
|
0xe4 0x17 0x7f 0xd3
|
|
0xc5 0xfc 0x4c 0xd3
|
|
|
|
# CHECK: bfi x4, x5, #52, #11
|
|
# CHECK: bfxil xzr, x4, #0, #1
|
|
# CHECK: bfi x4, xzr, #1, #6
|
|
# CHECK: bfxil x5, x6, #12, #52
|
|
0xa4 0x28 0x4c 0xb3
|
|
0x9f 0x0 0x40 0xb3
|
|
0xe4 0x17 0x7f 0xb3
|
|
0xc5 0xfc 0x4c 0xb3
|
|
|
|
# CHECK: sxtb w1, w2
|
|
# CHECK: sxtb xzr, w3
|
|
# CHECK: sxth w9, w10
|
|
# CHECK: sxth x0, w1
|
|
# CHECK: sxtw x3, w30
|
|
0x41 0x1c 0x0 0x13
|
|
0x7f 0x1c 0x40 0x93
|
|
0x49 0x3d 0x0 0x13
|
|
0x20 0x3c 0x40 0x93
|
|
0xc3 0x7f 0x40 0x93
|
|
|
|
# CHECK: uxtb w1, w2
|
|
# CHECK: uxth w9, w10
|
|
# CHECK: ubfx x3, x30, #0, #32
|
|
0x41 0x1c 0x0 0x53
|
|
0x49 0x3d 0x0 0x53
|
|
0xc3 0x7f 0x40 0xd3
|
|
|
|
# CHECK: asr w3, w2, #0
|
|
# CHECK: asr w9, w10, #31
|
|
# CHECK: asr x20, x21, #63
|
|
# CHECK: asr w1, wzr, #3
|
|
0x43 0x7c 0x0 0x13
|
|
0x49 0x7d 0x1f 0x13
|
|
0xb4 0xfe 0x7f 0x93
|
|
0xe1 0x7f 0x3 0x13
|
|
|
|
# CHECK: lsr w3, w2, #0
|
|
# CHECK: lsr w9, w10, #31
|
|
# CHECK: lsr x20, x21, #63
|
|
# CHECK: lsr wzr, wzr, #3
|
|
0x43 0x7c 0x0 0x53
|
|
0x49 0x7d 0x1f 0x53
|
|
0xb4 0xfe 0x7f 0xd3
|
|
0xff 0x7f 0x3 0x53
|
|
|
|
# CHECK: lsr w3, w2, #0
|
|
# CHECK: lsl w9, w10, #31
|
|
# CHECK: lsl x20, x21, #63
|
|
# CHECK: lsl w1, wzr, #3
|
|
0x43 0x7c 0x0 0x53
|
|
0x49 0x1 0x1 0x53
|
|
0xb4 0x2 0x41 0xd3
|
|
0xe1 0x73 0x1d 0x53
|
|
|
|
# CHECK: sbfx w9, w10, #0, #1
|
|
# CHECK: sbfiz x2, x3, #63, #1
|
|
# CHECK: asr x19, x20, #0
|
|
# CHECK: sbfiz x9, x10, #5, #59
|
|
# CHECK: asr w9, w10, #0
|
|
# CHECK: sbfiz w11, w12, #31, #1
|
|
# CHECK: sbfiz w13, w14, #29, #3
|
|
# CHECK: sbfiz xzr, xzr, #10, #11
|
|
0x49 0x1 0x0 0x13
|
|
0x62 0x0 0x41 0x93
|
|
0x93 0xfe 0x40 0x93
|
|
0x49 0xe9 0x7b 0x93
|
|
0x49 0x7d 0x0 0x13
|
|
0x8b 0x1 0x1 0x13
|
|
0xcd 0x9 0x3 0x13
|
|
0xff 0x2b 0x76 0x93
|
|
|
|
# CHECK: sbfx w9, w10, #0, #1
|
|
# CHECK: asr x2, x3, #63
|
|
# CHECK: asr x19, x20, #0
|
|
# CHECK: asr x9, x10, #5
|
|
# CHECK: asr w9, w10, #0
|
|
# CHECK: asr w11, w12, #31
|
|
# CHECK: asr w13, w14, #29
|
|
# CHECK: sbfx xzr, xzr, #10, #11
|
|
0x49 0x1 0x0 0x13
|
|
0x62 0xfc 0x7f 0x93
|
|
0x93 0xfe 0x40 0x93
|
|
0x49 0xfd 0x45 0x93
|
|
0x49 0x7d 0x0 0x13
|
|
0x8b 0x7d 0x1f 0x13
|
|
0xcd 0x7d 0x1d 0x13
|
|
0xff 0x53 0x4a 0x93
|
|
|
|
# CHECK: bfxil w9, w10, #0, #1
|
|
# CHECK: bfi x2, x3, #63, #1
|
|
# CHECK: bfxil x19, x20, #0, #64
|
|
# CHECK: bfi x9, x10, #5, #59
|
|
# CHECK: bfxil w9, w10, #0, #32
|
|
# CHECK: bfi w11, w12, #31, #1
|
|
# CHECK: bfi w13, w14, #29, #3
|
|
# CHECK: bfi xzr, xzr, #10, #11
|
|
0x49 0x1 0x0 0x33
|
|
0x62 0x0 0x41 0xb3
|
|
0x93 0xfe 0x40 0xb3
|
|
0x49 0xe9 0x7b 0xb3
|
|
0x49 0x7d 0x0 0x33
|
|
0x8b 0x1 0x1 0x33
|
|
0xcd 0x9 0x3 0x33
|
|
0xff 0x2b 0x76 0xb3
|
|
|
|
# CHECK: bfxil w9, w10, #0, #1
|
|
# CHECK: bfxil x2, x3, #63, #1
|
|
# CHECK: bfxil x19, x20, #0, #64
|
|
# CHECK: bfxil x9, x10, #5, #59
|
|
# CHECK: bfxil w9, w10, #0, #32
|
|
# CHECK: bfxil w11, w12, #31, #1
|
|
# CHECK: bfxil w13, w14, #29, #3
|
|
# CHECK: bfxil xzr, xzr, #10, #11
|
|
0x49 0x1 0x0 0x33
|
|
0x62 0xfc 0x7f 0xb3
|
|
0x93 0xfe 0x40 0xb3
|
|
0x49 0xfd 0x45 0xb3
|
|
0x49 0x7d 0x0 0x33
|
|
0x8b 0x7d 0x1f 0x33
|
|
0xcd 0x7d 0x1d 0x33
|
|
0xff 0x53 0x4a 0xb3
|
|
|
|
# CHECK: ubfx w9, w10, #0, #1
|
|
# CHECK: lsl x2, x3, #63
|
|
# CHECK: lsr x19, x20, #0
|
|
# CHECK: lsl x9, x10, #5
|
|
# CHECK: lsr w9, w10, #0
|
|
# CHECK: lsl w11, w12, #31
|
|
# CHECK: lsl w13, w14, #29
|
|
# CHECK: ubfiz xzr, xzr, #10, #11
|
|
0x49 0x1 0x0 0x53
|
|
0x62 0x0 0x41 0xd3
|
|
0x93 0xfe 0x40 0xd3
|
|
0x49 0xe9 0x7b 0xd3
|
|
0x49 0x7d 0x0 0x53
|
|
0x8b 0x1 0x1 0x53
|
|
0xcd 0x9 0x3 0x53
|
|
0xff 0x2b 0x76 0xd3
|
|
|
|
# CHECK: ubfx w9, w10, #0, #1
|
|
# CHECK: lsr x2, x3, #63
|
|
# CHECK: lsr x19, x20, #0
|
|
# CHECK: lsr x9, x10, #5
|
|
# CHECK: lsr w9, w10, #0
|
|
# CHECK: lsr w11, w12, #31
|
|
# CHECK: lsr w13, w14, #29
|
|
# CHECK: ubfx xzr, xzr, #10, #11
|
|
0x49 0x1 0x0 0x53
|
|
0x62 0xfc 0x7f 0xd3
|
|
0x93 0xfe 0x40 0xd3
|
|
0x49 0xfd 0x45 0xd3
|
|
0x49 0x7d 0x0 0x53
|
|
0x8b 0x7d 0x1f 0x53
|
|
0xcd 0x7d 0x1d 0x53
|
|
0xff 0x53 0x4a 0xd3
|
|
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Compare and branch (immediate)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: cbz w5, #4
|
|
# CHECK: cbz x5, #0
|
|
# CHECK: cbnz x2, #-4
|
|
# CHECK: cbnz x26, #1048572
|
|
0x25 0x0 0x0 0x34
|
|
0x05 0x0 0x0 0xb4
|
|
0xe2 0xff 0xff 0xb5
|
|
0xfa 0xff 0x7f 0xb5
|
|
|
|
# CHECK: cbz wzr, #0
|
|
# CHECK: cbnz xzr, #0
|
|
0x1f 0x0 0x0 0x34
|
|
0x1f 0x0 0x0 0xb5
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Conditional branch (immediate)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: b.ne #4
|
|
# CHECK: b.ge #1048572
|
|
# CHECK: b.ge #-4
|
|
0x21 0x00 0x00 0x54
|
|
0xea 0xff 0x7f 0x54
|
|
0xea 0xff 0xff 0x54
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Conditional compare (immediate)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: ccmp w1, #31, #0, eq
|
|
# CHECK: ccmp w3, #0, #15, hs
|
|
# CHECK: ccmp wzr, #15, #13, hs
|
|
0x20 0x08 0x5f 0x7a
|
|
0x6f 0x28 0x40 0x7a
|
|
0xed 0x2b 0x4f 0x7a
|
|
|
|
# CHECK: ccmp x9, #31, #0, le
|
|
# CHECK: ccmp x3, #0, #15, gt
|
|
# CHECK: ccmp xzr, #5, #7, ne
|
|
0x20 0xd9 0x5f 0xfa
|
|
0x6f 0xc8 0x40 0xfa
|
|
0xe7 0x1b 0x45 0xfa
|
|
|
|
# CHECK: ccmn w1, #31, #0, eq
|
|
# CHECK: ccmn w3, #0, #15, hs
|
|
# CHECK: ccmn wzr, #15, #13, hs
|
|
0x20 0x08 0x5f 0x3a
|
|
0x6f 0x28 0x40 0x3a
|
|
0xed 0x2b 0x4f 0x3a
|
|
|
|
# CHECK: ccmn x9, #31, #0, le
|
|
# CHECK: ccmn x3, #0, #15, gt
|
|
# CHECK: ccmn xzr, #5, #7, ne
|
|
0x20 0xd9 0x5f 0xba
|
|
0x6f 0xc8 0x40 0xba
|
|
0xe7 0x1b 0x45 0xba
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Conditional compare (register)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: ccmp w1, wzr, #0, eq
|
|
# CHECK: ccmp w3, w0, #15, hs
|
|
# CHECK: ccmp wzr, w15, #13, hs
|
|
0x20 0x00 0x5f 0x7a
|
|
0x6f 0x20 0x40 0x7a
|
|
0xed 0x23 0x4f 0x7a
|
|
|
|
# CHECK: ccmp x9, xzr, #0, le
|
|
# CHECK: ccmp x3, x0, #15, gt
|
|
# CHECK: ccmp xzr, x5, #7, ne
|
|
0x20 0xd1 0x5f 0xfa
|
|
0x6f 0xc0 0x40 0xfa
|
|
0xe7 0x13 0x45 0xfa
|
|
|
|
# CHECK: ccmn w1, wzr, #0, eq
|
|
# CHECK: ccmn w3, w0, #15, hs
|
|
# CHECK: ccmn wzr, w15, #13, hs
|
|
0x20 0x00 0x5f 0x3a
|
|
0x6f 0x20 0x40 0x3a
|
|
0xed 0x23 0x4f 0x3a
|
|
|
|
# CHECK: ccmn x9, xzr, #0, le
|
|
# CHECK: ccmn x3, x0, #15, gt
|
|
# CHECK: ccmn xzr, x5, #7, ne
|
|
0x20 0xd1 0x5f 0xba
|
|
0x6f 0xc0 0x40 0xba
|
|
0xe7 0x13 0x45 0xba
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Conditional branch (immediate)
|
|
#------------------------------------------------------------------------------
|
|
# CHECK: csel w1, w0, w19, ne
|
|
# CHECK: csel wzr, w5, w9, eq
|
|
# CHECK: csel w9, wzr, w30, gt
|
|
# CHECK: csel w1, w28, wzr, mi
|
|
# CHECK: csel x19, x23, x29, lt
|
|
# CHECK: csel xzr, x3, x4, ge
|
|
# CHECK: csel x5, xzr, x6, hs
|
|
# CHECK: csel x7, x8, xzr, lo
|
|
0x1 0x10 0x93 0x1a
|
|
0xbf 0x0 0x89 0x1a
|
|
0xe9 0xc3 0x9e 0x1a
|
|
0x81 0x43 0x9f 0x1a
|
|
0xf3 0xb2 0x9d 0x9a
|
|
0x7f 0xa0 0x84 0x9a
|
|
0xe5 0x23 0x86 0x9a
|
|
0x7 0x31 0x9f 0x9a
|
|
|
|
# CHECK: csinc w1, w0, w19, ne
|
|
# CHECK: csinc wzr, w5, w9, eq
|
|
# CHECK: csinc w9, wzr, w30, gt
|
|
# CHECK: csinc w1, w28, wzr, mi
|
|
# CHECK: csinc x19, x23, x29, lt
|
|
# CHECK: csinc xzr, x3, x4, ge
|
|
# CHECK: csinc x5, xzr, x6, hs
|
|
# CHECK: csinc x7, x8, xzr, lo
|
|
0x1 0x14 0x93 0x1a
|
|
0xbf 0x4 0x89 0x1a
|
|
0xe9 0xc7 0x9e 0x1a
|
|
0x81 0x47 0x9f 0x1a
|
|
0xf3 0xb6 0x9d 0x9a
|
|
0x7f 0xa4 0x84 0x9a
|
|
0xe5 0x27 0x86 0x9a
|
|
0x7 0x35 0x9f 0x9a
|
|
|
|
# CHECK: csinv w1, w0, w19, ne
|
|
# CHECK: csinv wzr, w5, w9, eq
|
|
# CHECK: csinv w9, wzr, w30, gt
|
|
# CHECK: csinv w1, w28, wzr, mi
|
|
# CHECK: csinv x19, x23, x29, lt
|
|
# CHECK: csinv xzr, x3, x4, ge
|
|
# CHECK: csinv x5, xzr, x6, hs
|
|
# CHECK: csinv x7, x8, xzr, lo
|
|
0x1 0x10 0x93 0x5a
|
|
0xbf 0x0 0x89 0x5a
|
|
0xe9 0xc3 0x9e 0x5a
|
|
0x81 0x43 0x9f 0x5a
|
|
0xf3 0xb2 0x9d 0xda
|
|
0x7f 0xa0 0x84 0xda
|
|
0xe5 0x23 0x86 0xda
|
|
0x7 0x31 0x9f 0xda
|
|
|
|
# CHECK: csneg w1, w0, w19, ne
|
|
# CHECK: csneg wzr, w5, w9, eq
|
|
# CHECK: csneg w9, wzr, w30, gt
|
|
# CHECK: csneg w1, w28, wzr, mi
|
|
# CHECK: csneg x19, x23, x29, lt
|
|
# CHECK: csneg xzr, x3, x4, ge
|
|
# CHECK: csneg x5, xzr, x6, hs
|
|
# CHECK: csneg x7, x8, xzr, lo
|
|
0x1 0x14 0x93 0x5a
|
|
0xbf 0x4 0x89 0x5a
|
|
0xe9 0xc7 0x9e 0x5a
|
|
0x81 0x47 0x9f 0x5a
|
|
0xf3 0xb6 0x9d 0xda
|
|
0x7f 0xa4 0x84 0xda
|
|
0xe5 0x27 0x86 0xda
|
|
0x7 0x35 0x9f 0xda
|
|
|
|
# CHECK: csinc w3, wzr, wzr, ne
|
|
# CHECK: csinc x9, xzr, xzr, mi
|
|
# CHECK: csinv w20, wzr, wzr, eq
|
|
# CHECK: csinv x30, xzr, xzr, lt
|
|
0xe3 0x17 0x9f 0x1a
|
|
0xe9 0x47 0x9f 0x9a
|
|
0xf4 0x3 0x9f 0x5a
|
|
0xfe 0xb3 0x9f 0xda
|
|
|
|
# CHECK: csinc w3, w5, w5, le
|
|
# CHECK: csinc wzr, w4, w4, gt
|
|
# CHECK: csinc w9, wzr, wzr, ge
|
|
# CHECK: csinc x3, x5, x5, le
|
|
# CHECK: csinc xzr, x4, x4, gt
|
|
# CHECK: csinc x9, xzr, xzr, ge
|
|
0xa3 0xd4 0x85 0x1a
|
|
0x9f 0xc4 0x84 0x1a
|
|
0xe9 0xa7 0x9f 0x1a
|
|
0xa3 0xd4 0x85 0x9a
|
|
0x9f 0xc4 0x84 0x9a
|
|
0xe9 0xa7 0x9f 0x9a
|
|
|
|
# CHECK: csinv w3, w5, w5, le
|
|
# CHECK: csinv wzr, w4, w4, gt
|
|
# CHECK: csinv w9, wzr, wzr, ge
|
|
# CHECK: csinv x3, x5, x5, le
|
|
# CHECK: csinv xzr, x4, x4, gt
|
|
# CHECK: csinv x9, xzr, xzr, ge
|
|
0xa3 0xd0 0x85 0x5a
|
|
0x9f 0xc0 0x84 0x5a
|
|
0xe9 0xa3 0x9f 0x5a
|
|
0xa3 0xd0 0x85 0xda
|
|
0x9f 0xc0 0x84 0xda
|
|
0xe9 0xa3 0x9f 0xda
|
|
|
|
# CHECK: csneg w3, w5, w5, le
|
|
# CHECK: csneg wzr, w4, w4, gt
|
|
# CHECK: csneg w9, wzr, wzr, ge
|
|
# CHECK: csneg x3, x5, x5, le
|
|
# CHECK: csneg xzr, x4, x4, gt
|
|
# CHECK: csneg x9, xzr, xzr, ge
|
|
0xa3 0xd4 0x85 0x5a
|
|
0x9f 0xc4 0x84 0x5a
|
|
0xe9 0xa7 0x9f 0x5a
|
|
0xa3 0xd4 0x85 0xda
|
|
0x9f 0xc4 0x84 0xda
|
|
0xe9 0xa7 0x9f 0xda
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Data-processing (1 source)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: rbit w0, w7
|
|
# CHECK: rbit x18, x3
|
|
# CHECK: rev16 w17, w1
|
|
# CHECK: rev16 x5, x2
|
|
# CHECK: rev w18, w0
|
|
# CHECK: rev32 x20, x1
|
|
0xe0 0x00 0xc0 0x5a
|
|
0x72 0x00 0xc0 0xda
|
|
0x31 0x04 0xc0 0x5a
|
|
0x45 0x04 0xc0 0xda
|
|
0x12 0x08 0xc0 0x5a
|
|
0x34 0x08 0xc0 0xda
|
|
|
|
# CHECK: rev x22, x2
|
|
# CHECK: clz w24, w3
|
|
# CHECK: clz x26, x4
|
|
# CHECK: cls w3, w5
|
|
# CHECK: cls x20, x5
|
|
0x56 0x0c 0xc0 0xda
|
|
0x78 0x10 0xc0 0x5a
|
|
0x9a 0x10 0xc0 0xda
|
|
0xa3 0x14 0xc0 0x5a
|
|
0xb4 0x14 0xc0 0xda
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Data-processing (2 source)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: crc32b w5, w7, w20
|
|
# CHECK: crc32h w28, wzr, w30
|
|
# CHECK: crc32w w0, w1, w2
|
|
# CHECK: crc32x w7, w9, x20
|
|
# CHECK: crc32cb w9, w5, w4
|
|
# CHECK: crc32ch w13, w17, w25
|
|
# CHECK: crc32cw wzr, w3, w5
|
|
# CHECK: crc32cx w18, w16, xzr
|
|
0xe5 0x40 0xd4 0x1a
|
|
0xfc 0x47 0xde 0x1a
|
|
0x20 0x48 0xc2 0x1a
|
|
0x27 0x4d 0xd4 0x9a
|
|
0xa9 0x50 0xc4 0x1a
|
|
0x2d 0x56 0xd9 0x1a
|
|
0x7f 0x58 0xc5 0x1a
|
|
0x12 0x5e 0xdf 0x9a
|
|
|
|
# CHECK: udiv w0, w7, w10
|
|
# CHECK: udiv x9, x22, x4
|
|
# CHECK: sdiv w12, w21, w0
|
|
# CHECK: sdiv x13, x2, x1
|
|
# CHECK: lsl w11, w12, w13
|
|
# CHECK: lsl x14, x15, x16
|
|
# CHECK: lsr w17, w18, w19
|
|
# CHECK: lsr x20, x21, x22
|
|
# CHECK: asr w23, w24, w25
|
|
# CHECK: asr x26, x27, x28
|
|
# CHECK: ror w0, w1, w2
|
|
# CHECK: ror x3, x4, x5
|
|
0xe0 0x08 0xca 0x1a
|
|
0xc9 0x0a 0xc4 0x9a
|
|
0xac 0x0e 0xc0 0x1a
|
|
0x4d 0x0c 0xc1 0x9a
|
|
0x8b 0x21 0xcd 0x1a
|
|
0xee 0x21 0xd0 0x9a
|
|
0x51 0x26 0xd3 0x1a
|
|
0xb4 0x26 0xd6 0x9a
|
|
0x17 0x2b 0xd9 0x1a
|
|
0x7a 0x2b 0xdc 0x9a
|
|
0x20 0x2c 0xc2 0x1a
|
|
0x83 0x2c 0xc5 0x9a
|
|
|
|
# CHECK: lsl w6, w7, w8
|
|
# CHECK: lsl x9, x10, x11
|
|
# CHECK: lsr w12, w13, w14
|
|
# CHECK: lsr x15, x16, x17
|
|
# CHECK: asr w18, w19, w20
|
|
# CHECK: asr x21, x22, x23
|
|
# CHECK: ror w24, w25, w26
|
|
# CHECK: ror x27, x28, x29
|
|
0xe6 0x20 0xc8 0x1a
|
|
0x49 0x21 0xcb 0x9a
|
|
0xac 0x25 0xce 0x1a
|
|
0x0f 0x26 0xd1 0x9a
|
|
0x72 0x2a 0xd4 0x1a
|
|
0xd5 0x2a 0xd7 0x9a
|
|
0x38 0x2f 0xda 0x1a
|
|
0x9b 0x2f 0xdd 0x9a
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Data-processing (3 sources)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# First check some non-canonical encodings where Ra is not 0b11111 (only umulh
|
|
# and smulh have them).
|
|
|
|
# CHECK: smulh x30, x29, x28
|
|
# CHECK: smulh xzr, x27, x26
|
|
# CHECK: umulh x30, x29, x28
|
|
# CHECK: umulh x23, x30, xzr
|
|
0xbe 0x73 0x5c 0x9b
|
|
0x7f 0x2f 0x5a 0x9b
|
|
0xbe 0x3f 0xdc 0x9b
|
|
0xd7 0x77 0xdf 0x9b
|
|
|
|
# Now onto the boilerplate stuff
|
|
|
|
# CHECK: madd w1, w3, w7, w4
|
|
# CHECK: madd wzr, w0, w9, w11
|
|
# CHECK: madd w13, wzr, w4, w4
|
|
# CHECK: madd w19, w30, wzr, w29
|
|
# CHECK: mul w4, w5, w6
|
|
0x61 0x10 0x7 0x1b
|
|
0x1f 0x2c 0x9 0x1b
|
|
0xed 0x13 0x4 0x1b
|
|
0xd3 0x77 0x1f 0x1b
|
|
0xa4 0x7c 0x6 0x1b
|
|
|
|
# CHECK: madd x1, x3, x7, x4
|
|
# CHECK: madd xzr, x0, x9, x11
|
|
# CHECK: madd x13, xzr, x4, x4
|
|
# CHECK: madd x19, x30, xzr, x29
|
|
# CHECK: mul x4, x5, x6
|
|
0x61 0x10 0x7 0x9b
|
|
0x1f 0x2c 0x9 0x9b
|
|
0xed 0x13 0x4 0x9b
|
|
0xd3 0x77 0x1f 0x9b
|
|
0xa4 0x7c 0x6 0x9b
|
|
|
|
# CHECK: msub w1, w3, w7, w4
|
|
# CHECK: msub wzr, w0, w9, w11
|
|
# CHECK: msub w13, wzr, w4, w4
|
|
# CHECK: msub w19, w30, wzr, w29
|
|
# CHECK: mneg w4, w5, w6
|
|
0x61 0x90 0x7 0x1b
|
|
0x1f 0xac 0x9 0x1b
|
|
0xed 0x93 0x4 0x1b
|
|
0xd3 0xf7 0x1f 0x1b
|
|
0xa4 0xfc 0x6 0x1b
|
|
|
|
# CHECK: msub x1, x3, x7, x4
|
|
# CHECK: msub xzr, x0, x9, x11
|
|
# CHECK: msub x13, xzr, x4, x4
|
|
# CHECK: msub x19, x30, xzr, x29
|
|
# CHECK: mneg x4, x5, x6
|
|
0x61 0x90 0x7 0x9b
|
|
0x1f 0xac 0x9 0x9b
|
|
0xed 0x93 0x4 0x9b
|
|
0xd3 0xf7 0x1f 0x9b
|
|
0xa4 0xfc 0x6 0x9b
|
|
|
|
# CHECK: smaddl x3, w5, w2, x9
|
|
# CHECK: smaddl xzr, w10, w11, x12
|
|
# CHECK: smaddl x13, wzr, w14, x15
|
|
# CHECK: smaddl x16, w17, wzr, x18
|
|
# CHECK: smull x19, w20, w21
|
|
0xa3 0x24 0x22 0x9b
|
|
0x5f 0x31 0x2b 0x9b
|
|
0xed 0x3f 0x2e 0x9b
|
|
0x30 0x4a 0x3f 0x9b
|
|
0x93 0x7e 0x35 0x9b
|
|
|
|
# CHECK: smsubl x3, w5, w2, x9
|
|
# CHECK: smsubl xzr, w10, w11, x12
|
|
# CHECK: smsubl x13, wzr, w14, x15
|
|
# CHECK: smsubl x16, w17, wzr, x18
|
|
# CHECK: smnegl x19, w20, w21
|
|
0xa3 0xa4 0x22 0x9b
|
|
0x5f 0xb1 0x2b 0x9b
|
|
0xed 0xbf 0x2e 0x9b
|
|
0x30 0xca 0x3f 0x9b
|
|
0x93 0xfe 0x35 0x9b
|
|
|
|
# CHECK: umaddl x3, w5, w2, x9
|
|
# CHECK: umaddl xzr, w10, w11, x12
|
|
# CHECK: umaddl x13, wzr, w14, x15
|
|
# CHECK: umaddl x16, w17, wzr, x18
|
|
# CHECK: umull x19, w20, w21
|
|
0xa3 0x24 0xa2 0x9b
|
|
0x5f 0x31 0xab 0x9b
|
|
0xed 0x3f 0xae 0x9b
|
|
0x30 0x4a 0xbf 0x9b
|
|
0x93 0x7e 0xb5 0x9b
|
|
|
|
# CHECK: umsubl x3, w5, w2, x9
|
|
# CHECK: umsubl xzr, w10, w11, x12
|
|
# CHECK: umsubl x13, wzr, w14, x15
|
|
# CHECK: umsubl x16, w17, wzr, x18
|
|
# CHECK: umnegl x19, w20, w21
|
|
0xa3 0xa4 0xa2 0x9b
|
|
0x5f 0xb1 0xab 0x9b
|
|
0xed 0xbf 0xae 0x9b
|
|
0x30 0xca 0xbf 0x9b
|
|
0x93 0xfe 0xb5 0x9b
|
|
|
|
# CHECK: smulh x30, x29, x28
|
|
# CHECK: smulh xzr, x27, x26
|
|
# CHECK: smulh x25, xzr, x24
|
|
# CHECK: smulh x23, x22, xzr
|
|
0xbe 0x7f 0x5c 0x9b
|
|
0x7f 0x7f 0x5a 0x9b
|
|
0xf9 0x7f 0x58 0x9b
|
|
0xd7 0x7e 0x5f 0x9b
|
|
|
|
# CHECK: umulh x30, x29, x28
|
|
# CHECK: umulh xzr, x27, x26
|
|
# CHECK: umulh x25, xzr, x24
|
|
# CHECK: umulh x23, x22, xzr
|
|
0xbe 0x7f 0xdc 0x9b
|
|
0x7f 0x7f 0xda 0x9b
|
|
0xf9 0x7f 0xd8 0x9b
|
|
0xd7 0x7e 0xdf 0x9b
|
|
|
|
# CHECK: mul w3, w4, w5
|
|
# CHECK: mul wzr, w6, w7
|
|
# CHECK: mul w8, wzr, w9
|
|
# CHECK: mul w10, w11, wzr
|
|
# CHECK: mul x12, x13, x14
|
|
# CHECK: mul xzr, x15, x16
|
|
# CHECK: mul x17, xzr, x18
|
|
# CHECK: mul x19, x20, xzr
|
|
0x83 0x7c 0x5 0x1b
|
|
0xdf 0x7c 0x7 0x1b
|
|
0xe8 0x7f 0x9 0x1b
|
|
0x6a 0x7d 0x1f 0x1b
|
|
0xac 0x7d 0xe 0x9b
|
|
0xff 0x7d 0x10 0x9b
|
|
0xf1 0x7f 0x12 0x9b
|
|
0x93 0x7e 0x1f 0x9b
|
|
|
|
# CHECK: mneg w21, w22, w23
|
|
# CHECK: mneg wzr, w24, w25
|
|
# CHECK: mneg w26, wzr, w27
|
|
# CHECK: mneg w28, w29, wzr
|
|
0xd5 0xfe 0x17 0x1b
|
|
0x1f 0xff 0x19 0x1b
|
|
0xfa 0xff 0x1b 0x1b
|
|
0xbc 0xff 0x1f 0x1b
|
|
|
|
# CHECK: smull x11, w13, w17
|
|
# CHECK: umull x11, w13, w17
|
|
# CHECK: smnegl x11, w13, w17
|
|
# CHECK: umnegl x11, w13, w17
|
|
0xab 0x7d 0x31 0x9b
|
|
0xab 0x7d 0xb1 0x9b
|
|
0xab 0xfd 0x31 0x9b
|
|
0xab 0xfd 0xb1 0x9b
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Exception generation
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: svc #0
|
|
# CHECK: svc #{{65535|0xffff}}
|
|
0x1 0x0 0x0 0xd4
|
|
0xe1 0xff 0x1f 0xd4
|
|
|
|
# CHECK: hvc #{{1|0x1}}
|
|
# CHECK: smc #{{12000|0x2ee0}}
|
|
# CHECK: brk #{{12|0xc}}
|
|
# CHECK: hlt #{{123|0x7b}}
|
|
0x22 0x0 0x0 0xd4
|
|
0x3 0xdc 0x5 0xd4
|
|
0x80 0x1 0x20 0xd4
|
|
0x60 0xf 0x40 0xd4
|
|
|
|
# CHECK: dcps1 #{{42|0x2a}}
|
|
# CHECK: dcps2 #{{9|0x9}}
|
|
# CHECK: dcps3 #{{1000|0x3e8}}
|
|
0x41 0x5 0xa0 0xd4
|
|
0x22 0x1 0xa0 0xd4
|
|
0x3 0x7d 0xa0 0xd4
|
|
|
|
# CHECK: dcps1
|
|
# CHECK: dcps2
|
|
# CHECK: dcps3
|
|
0x1 0x0 0xa0 0xd4
|
|
0x2 0x0 0xa0 0xd4
|
|
0x3 0x0 0xa0 0xd4
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Extract (immediate)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: extr w3, w5, w7, #0
|
|
# CHECK: extr w11, w13, w17, #31
|
|
0xa3 0x0 0x87 0x13
|
|
0xab 0x7d 0x91 0x13
|
|
|
|
# CHECK: extr x3, x5, x7, #15
|
|
# CHECK: extr x11, x13, x17, #63
|
|
0xa3 0x3c 0xc7 0x93
|
|
0xab 0xfd 0xd1 0x93
|
|
|
|
# CHECK: extr x19, x23, x23, #24
|
|
# CHECK: extr x29, xzr, xzr, #63
|
|
# CHECK: extr w9, w13, w13, #31
|
|
0xf3 0x62 0xd7 0x93
|
|
0xfd 0xff 0xdf 0x93
|
|
0xa9 0x7d 0x8d 0x13
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Floating-point compare
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: fcmp s3, s5
|
|
# CHECK: fcmp s31, #0.0
|
|
# CHECK: fcmp s31, #0.0
|
|
0x60 0x20 0x25 0x1e
|
|
0xe8 0x23 0x20 0x1e
|
|
0xe8 0x23 0x3f 0x1e
|
|
|
|
# CHECK: fcmpe s29, s30
|
|
# CHECK: fcmpe s15, #0.0
|
|
# CHECK: fcmpe s15, #0.0
|
|
0xb0 0x23 0x3e 0x1e
|
|
0xf8 0x21 0x20 0x1e
|
|
0xf8 0x21 0x2f 0x1e
|
|
|
|
# CHECK: fcmp d4, d12
|
|
# CHECK: fcmp d23, #0.0
|
|
# CHECK: fcmp d23, #0.0
|
|
0x80 0x20 0x6c 0x1e
|
|
0xe8 0x22 0x60 0x1e
|
|
0xe8 0x22 0x77 0x1e
|
|
|
|
# CHECK: fcmpe d26, d22
|
|
# CHECK: fcmpe d29, #0.0
|
|
# CHECK: fcmpe d29, #0.0
|
|
0x50 0x23 0x76 0x1e
|
|
0xb8 0x23 0x60 0x1e
|
|
0xb8 0x23 0x6d 0x1e
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Floating-point conditional compare
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: fccmp s1, s31, #0, eq
|
|
# CHECK: fccmp s3, s0, #15, hs
|
|
# CHECK: fccmp s31, s15, #13, hs
|
|
0x20 0x04 0x3f 0x1e
|
|
0x6f 0x24 0x20 0x1e
|
|
0xed 0x27 0x2f 0x1e
|
|
|
|
# CHECK: fccmp d9, d31, #0, le
|
|
# CHECK: fccmp d3, d0, #15, gt
|
|
# CHECK: fccmp d31, d5, #7, ne
|
|
0x20 0xd5 0x7f 0x1e
|
|
0x6f 0xc4 0x60 0x1e
|
|
0xe7 0x17 0x65 0x1e
|
|
|
|
# CHECK: fccmpe s1, s31, #0, eq
|
|
# CHECK: fccmpe s3, s0, #15, hs
|
|
# CHECK: fccmpe s31, s15, #13, hs
|
|
0x30 0x04 0x3f 0x1e
|
|
0x7f 0x24 0x20 0x1e
|
|
0xfd 0x27 0x2f 0x1e
|
|
|
|
# CHECK: fccmpe d9, d31, #0, le
|
|
# CHECK: fccmpe d3, d0, #15, gt
|
|
# CHECK: fccmpe d31, d5, #7, ne
|
|
0x30 0xd5 0x7f 0x1e
|
|
0x7f 0xc4 0x60 0x1e
|
|
0xf7 0x17 0x65 0x1e
|
|
|
|
#-------------------------------------------------------------------------------
|
|
# Floating-point conditional compare
|
|
#-------------------------------------------------------------------------------
|
|
|
|
# CHECK: fcsel s3, s20, s9, pl
|
|
# CHECK: fcsel d9, d10, d11, mi
|
|
0x83 0x5e 0x29 0x1e
|
|
0x49 0x4d 0x6b 0x1e
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Floating-point data-processing (1 source)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: fmov s0, s1
|
|
# CHECK: fabs s2, s3
|
|
# CHECK: fneg s4, s5
|
|
# CHECK: fsqrt s6, s7
|
|
# CHECK: fcvt d8, s9
|
|
# CHECK: fcvt h10, s11
|
|
# CHECK: frintn s12, s13
|
|
# CHECK: frintp s14, s15
|
|
# CHECK: frintm s16, s17
|
|
# CHECK: frintz s18, s19
|
|
# CHECK: frinta s20, s21
|
|
# CHECK: frintx s22, s23
|
|
# CHECK: frinti s24, s25
|
|
0x20 0x40 0x20 0x1e
|
|
0x62 0xc0 0x20 0x1e
|
|
0xa4 0x40 0x21 0x1e
|
|
0xe6 0xc0 0x21 0x1e
|
|
0x28 0xc1 0x22 0x1e
|
|
0x6a 0xc1 0x23 0x1e
|
|
0xac 0x41 0x24 0x1e
|
|
0xee 0xc1 0x24 0x1e
|
|
0x30 0x42 0x25 0x1e
|
|
0x72 0xc2 0x25 0x1e
|
|
0xb4 0x42 0x26 0x1e
|
|
0xf6 0x42 0x27 0x1e
|
|
0x38 0xc3 0x27 0x1e
|
|
|
|
# CHECK: fmov d0, d1
|
|
# CHECK: fabs d2, d3
|
|
# CHECK: fneg d4, d5
|
|
# CHECK: fsqrt d6, d7
|
|
# CHECK: fcvt s8, d9
|
|
# CHECK: fcvt h10, d11
|
|
# CHECK: frintn d12, d13
|
|
# CHECK: frintp d14, d15
|
|
# CHECK: frintm d16, d17
|
|
# CHECK: frintz d18, d19
|
|
# CHECK: frinta d20, d21
|
|
# CHECK: frintx d22, d23
|
|
# CHECK: frinti d24, d25
|
|
0x20 0x40 0x60 0x1e
|
|
0x62 0xc0 0x60 0x1e
|
|
0xa4 0x40 0x61 0x1e
|
|
0xe6 0xc0 0x61 0x1e
|
|
0x28 0x41 0x62 0x1e
|
|
0x6a 0xc1 0x63 0x1e
|
|
0xac 0x41 0x64 0x1e
|
|
0xee 0xc1 0x64 0x1e
|
|
0x30 0x42 0x65 0x1e
|
|
0x72 0xc2 0x65 0x1e
|
|
0xb4 0x42 0x66 0x1e
|
|
0xf6 0x42 0x67 0x1e
|
|
0x38 0xc3 0x67 0x1e
|
|
|
|
# CHECK: fcvt s26, h27
|
|
# CHECK: fcvt d28, h29
|
|
0x7a 0x43 0xe2 0x1e
|
|
0xbc 0xc3 0xe2 0x1e
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Floating-point data-processing (2 sources)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: fmul s20, s19, s17
|
|
# CHECK: fdiv s1, s2, s3
|
|
# CHECK: fadd s4, s5, s6
|
|
# CHECK: fsub s7, s8, s9
|
|
# CHECK: fmax s10, s11, s12
|
|
# CHECK: fmin s13, s14, s15
|
|
# CHECK: fmaxnm s16, s17, s18
|
|
# CHECK: fminnm s19, s20, s21
|
|
# CHECK: fnmul s22, s23, s2
|
|
0x74 0xa 0x31 0x1e
|
|
0x41 0x18 0x23 0x1e
|
|
0xa4 0x28 0x26 0x1e
|
|
0x7 0x39 0x29 0x1e
|
|
0x6a 0x49 0x2c 0x1e
|
|
0xcd 0x59 0x2f 0x1e
|
|
0x30 0x6a 0x32 0x1e
|
|
0x93 0x7a 0x35 0x1e
|
|
0xf6 0x8a 0x38 0x1e
|
|
|
|
|
|
# CHECK: fmul d20, d19, d17
|
|
# CHECK: fdiv d1, d2, d3
|
|
# CHECK: fadd d4, d5, d6
|
|
# CHECK: fsub d7, d8, d9
|
|
# CHECK: fmax d10, d11, d12
|
|
# CHECK: fmin d13, d14, d15
|
|
# CHECK: fmaxnm d16, d17, d18
|
|
# CHECK: fminnm d19, d20, d21
|
|
# CHECK: fnmul d22, d23, d24
|
|
0x74 0xa 0x71 0x1e
|
|
0x41 0x18 0x63 0x1e
|
|
0xa4 0x28 0x66 0x1e
|
|
0x7 0x39 0x69 0x1e
|
|
0x6a 0x49 0x6c 0x1e
|
|
0xcd 0x59 0x6f 0x1e
|
|
0x30 0x6a 0x72 0x1e
|
|
0x93 0x7a 0x75 0x1e
|
|
0xf6 0x8a 0x78 0x1e
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Floating-point data-processing (1 source)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: fmadd s3, s5, s6, s31
|
|
# CHECK: fmadd d3, d13, d0, d23
|
|
# CHECK: fmsub s3, s5, s6, s31
|
|
# CHECK: fmsub d3, d13, d0, d23
|
|
# CHECK: fnmadd s3, s5, s6, s31
|
|
# CHECK: fnmadd d3, d13, d0, d23
|
|
# CHECK: fnmsub s3, s5, s6, s31
|
|
# CHECK: fnmsub d3, d13, d0, d23
|
|
0xa3 0x7c 0x06 0x1f
|
|
0xa3 0x5d 0x40 0x1f
|
|
0xa3 0xfc 0x06 0x1f
|
|
0xa3 0xdd 0x40 0x1f
|
|
0xa3 0x7c 0x26 0x1f
|
|
0xa3 0x5d 0x60 0x1f
|
|
0xa3 0xfc 0x26 0x1f
|
|
0xa3 0xdd 0x60 0x1f
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Floating-point <-> fixed-point conversion
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: fcvtzs w3, s5, #1
|
|
# CHECK: fcvtzs wzr, s20, #13
|
|
# CHECK: fcvtzs w19, s0, #32
|
|
0xa3 0xfc 0x18 0x1e
|
|
0x9f 0xce 0x18 0x1e
|
|
0x13 0x80 0x18 0x1e
|
|
|
|
# CHECK: fcvtzs x3, s5, #1
|
|
# CHECK: fcvtzs x12, s30, #45
|
|
# CHECK: fcvtzs x19, s0, #64
|
|
0xa3 0xfc 0x18 0x9e
|
|
0xcc 0x4f 0x18 0x9e
|
|
0x13 0x00 0x18 0x9e
|
|
|
|
# CHECK: fcvtzs w3, d5, #1
|
|
# CHECK: fcvtzs wzr, d20, #13
|
|
# CHECK: fcvtzs w19, d0, #32
|
|
0xa3 0xfc 0x58 0x1e
|
|
0x9f 0xce 0x58 0x1e
|
|
0x13 0x80 0x58 0x1e
|
|
|
|
# CHECK: fcvtzs x3, d5, #1
|
|
# CHECK: fcvtzs x12, d30, #45
|
|
# CHECK: fcvtzs x19, d0, #64
|
|
0xa3 0xfc 0x58 0x9e
|
|
0xcc 0x4f 0x58 0x9e
|
|
0x13 0x00 0x58 0x9e
|
|
|
|
# CHECK: fcvtzu w3, s5, #1
|
|
# CHECK: fcvtzu wzr, s20, #13
|
|
# CHECK: fcvtzu w19, s0, #32
|
|
0xa3 0xfc 0x19 0x1e
|
|
0x9f 0xce 0x19 0x1e
|
|
0x13 0x80 0x19 0x1e
|
|
|
|
# CHECK: fcvtzu x3, s5, #1
|
|
# CHECK: fcvtzu x12, s30, #45
|
|
# CHECK: fcvtzu x19, s0, #64
|
|
0xa3 0xfc 0x19 0x9e
|
|
0xcc 0x4f 0x19 0x9e
|
|
0x13 0x00 0x19 0x9e
|
|
|
|
# CHECK: fcvtzu w3, d5, #1
|
|
# CHECK: fcvtzu wzr, d20, #13
|
|
# CHECK: fcvtzu w19, d0, #32
|
|
0xa3 0xfc 0x59 0x1e
|
|
0x9f 0xce 0x59 0x1e
|
|
0x13 0x80 0x59 0x1e
|
|
|
|
# CHECK: fcvtzu x3, d5, #1
|
|
# CHECK: fcvtzu x12, d30, #45
|
|
# CHECK: fcvtzu x19, d0, #64
|
|
0xa3 0xfc 0x59 0x9e
|
|
0xcc 0x4f 0x59 0x9e
|
|
0x13 0x00 0x59 0x9e
|
|
|
|
# CHECK: scvtf s23, w19, #1
|
|
# CHECK: scvtf s31, wzr, #20
|
|
# CHECK: scvtf s14, w0, #32
|
|
0x77 0xfe 0x02 0x1e
|
|
0xff 0xb3 0x02 0x1e
|
|
0x0e 0x80 0x02 0x1e
|
|
|
|
# CHECK: scvtf s23, x19, #1
|
|
# CHECK: scvtf s31, xzr, #20
|
|
# CHECK: scvtf s14, x0, #64
|
|
0x77 0xfe 0x02 0x9e
|
|
0xff 0xb3 0x02 0x9e
|
|
0x0e 0x00 0x02 0x9e
|
|
|
|
# CHECK: scvtf d23, w19, #1
|
|
# CHECK: scvtf d31, wzr, #20
|
|
# CHECK: scvtf d14, w0, #32
|
|
0x77 0xfe 0x42 0x1e
|
|
0xff 0xb3 0x42 0x1e
|
|
0x0e 0x80 0x42 0x1e
|
|
|
|
# CHECK: scvtf d23, x19, #1
|
|
# CHECK: scvtf d31, xzr, #20
|
|
# CHECK: scvtf d14, x0, #64
|
|
0x77 0xfe 0x42 0x9e
|
|
0xff 0xb3 0x42 0x9e
|
|
0x0e 0x00 0x42 0x9e
|
|
|
|
# CHECK: ucvtf s23, w19, #1
|
|
# CHECK: ucvtf s31, wzr, #20
|
|
# CHECK: ucvtf s14, w0, #32
|
|
0x77 0xfe 0x03 0x1e
|
|
0xff 0xb3 0x03 0x1e
|
|
0x0e 0x80 0x03 0x1e
|
|
|
|
# CHECK: ucvtf s23, x19, #1
|
|
# CHECK: ucvtf s31, xzr, #20
|
|
# CHECK: ucvtf s14, x0, #64
|
|
0x77 0xfe 0x03 0x9e
|
|
0xff 0xb3 0x03 0x9e
|
|
0x0e 0x00 0x03 0x9e
|
|
|
|
# CHECK: ucvtf d23, w19, #1
|
|
# CHECK: ucvtf d31, wzr, #20
|
|
# CHECK: ucvtf d14, w0, #32
|
|
0x77 0xfe 0x43 0x1e
|
|
0xff 0xb3 0x43 0x1e
|
|
0x0e 0x80 0x43 0x1e
|
|
|
|
# CHECK: ucvtf d23, x19, #1
|
|
# CHECK: ucvtf d31, xzr, #20
|
|
# CHECK: ucvtf d14, x0, #64
|
|
0x77 0xfe 0x43 0x9e
|
|
0xff 0xb3 0x43 0x9e
|
|
0x0e 0x00 0x43 0x9e
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Floating-point <-> integer conversion
|
|
#------------------------------------------------------------------------------
|
|
# CHECK: fcvtns w3, s31
|
|
# CHECK: fcvtns xzr, s12
|
|
# CHECK: fcvtnu wzr, s12
|
|
# CHECK: fcvtnu x0, s0
|
|
0xe3 0x3 0x20 0x1e
|
|
0x9f 0x1 0x20 0x9e
|
|
0x9f 0x1 0x21 0x1e
|
|
0x0 0x0 0x21 0x9e
|
|
|
|
# CHECK: fcvtps wzr, s9
|
|
# CHECK: fcvtps x12, s20
|
|
# CHECK: fcvtpu w30, s23
|
|
# CHECK: fcvtpu x29, s3
|
|
0x3f 0x1 0x28 0x1e
|
|
0x8c 0x2 0x28 0x9e
|
|
0xfe 0x2 0x29 0x1e
|
|
0x7d 0x0 0x29 0x9e
|
|
|
|
# CHECK: fcvtms w2, s3
|
|
# CHECK: fcvtms x4, s5
|
|
# CHECK: fcvtmu w6, s7
|
|
# CHECK: fcvtmu x8, s9
|
|
0x62 0x0 0x30 0x1e
|
|
0xa4 0x0 0x30 0x9e
|
|
0xe6 0x0 0x31 0x1e
|
|
0x28 0x1 0x31 0x9e
|
|
|
|
# CHECK: fcvtzs w10, s11
|
|
# CHECK: fcvtzs x12, s13
|
|
# CHECK: fcvtzu w14, s15
|
|
# CHECK: fcvtzu x15, s16
|
|
0x6a 0x1 0x38 0x1e
|
|
0xac 0x1 0x38 0x9e
|
|
0xee 0x1 0x39 0x1e
|
|
0xf 0x2 0x39 0x9e
|
|
|
|
# CHECK: scvtf s17, w18
|
|
# CHECK: scvtf s19, x20
|
|
# CHECK: ucvtf s21, w22
|
|
# CHECK: scvtf s23, x24
|
|
0x51 0x2 0x22 0x1e
|
|
0x93 0x2 0x22 0x9e
|
|
0xd5 0x2 0x23 0x1e
|
|
0x17 0x3 0x22 0x9e
|
|
|
|
# CHECK: fcvtas w25, s26
|
|
# CHECK: fcvtas x27, s28
|
|
# CHECK: fcvtau w29, s30
|
|
# CHECK: fcvtau xzr, s0
|
|
0x59 0x3 0x24 0x1e
|
|
0x9b 0x3 0x24 0x9e
|
|
0xdd 0x3 0x25 0x1e
|
|
0x1f 0x0 0x25 0x9e
|
|
|
|
# CHECK: fcvtns w3, d31
|
|
# CHECK: fcvtns xzr, d12
|
|
# CHECK: fcvtnu wzr, d12
|
|
# CHECK: fcvtnu x0, d0
|
|
0xe3 0x3 0x60 0x1e
|
|
0x9f 0x1 0x60 0x9e
|
|
0x9f 0x1 0x61 0x1e
|
|
0x0 0x0 0x61 0x9e
|
|
|
|
# CHECK: fcvtps wzr, d9
|
|
# CHECK: fcvtps x12, d20
|
|
# CHECK: fcvtpu w30, d23
|
|
# CHECK: fcvtpu x29, d3
|
|
0x3f 0x1 0x68 0x1e
|
|
0x8c 0x2 0x68 0x9e
|
|
0xfe 0x2 0x69 0x1e
|
|
0x7d 0x0 0x69 0x9e
|
|
|
|
# CHECK: fcvtms w2, d3
|
|
# CHECK: fcvtms x4, d5
|
|
# CHECK: fcvtmu w6, d7
|
|
# CHECK: fcvtmu x8, d9
|
|
0x62 0x0 0x70 0x1e
|
|
0xa4 0x0 0x70 0x9e
|
|
0xe6 0x0 0x71 0x1e
|
|
0x28 0x1 0x71 0x9e
|
|
|
|
# CHECK: fcvtzs w10, d11
|
|
# CHECK: fcvtzs x12, d13
|
|
# CHECK: fcvtzu w14, d15
|
|
# CHECK: fcvtzu x15, d16
|
|
0x6a 0x1 0x78 0x1e
|
|
0xac 0x1 0x78 0x9e
|
|
0xee 0x1 0x79 0x1e
|
|
0xf 0x2 0x79 0x9e
|
|
|
|
# CHECK: scvtf d17, w18
|
|
# CHECK: scvtf d19, x20
|
|
# CHECK: ucvtf d21, w22
|
|
# CHECK: ucvtf d23, x24
|
|
0x51 0x2 0x62 0x1e
|
|
0x93 0x2 0x62 0x9e
|
|
0xd5 0x2 0x63 0x1e
|
|
0x17 0x3 0x63 0x9e
|
|
|
|
# CHECK: fcvtas w25, d26
|
|
# CHECK: fcvtas x27, d28
|
|
# CHECK: fcvtau w29, d30
|
|
# CHECK: fcvtau xzr, d0
|
|
0x59 0x3 0x64 0x1e
|
|
0x9b 0x3 0x64 0x9e
|
|
0xdd 0x3 0x65 0x1e
|
|
0x1f 0x0 0x65 0x9e
|
|
|
|
# CHECK: fmov w3, s9
|
|
# CHECK: fmov s9, w3
|
|
0x23 0x1 0x26 0x1e
|
|
0x69 0x0 0x27 0x1e
|
|
|
|
# CHECK: fmov x20, d31
|
|
# CHECK: fmov d1, x15
|
|
0xf4 0x3 0x66 0x9e
|
|
0xe1 0x1 0x67 0x9e
|
|
|
|
# CHECK: fmov x3, v12.d[1]
|
|
# CHECK: fmov v1.d[1], x19
|
|
0x83 0x1 0xae 0x9e
|
|
0x61 0x2 0xaf 0x9e
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Floating-point immediate
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: fmov s2, #0.12500000
|
|
# CHECK: fmov s3, #1.00000000
|
|
# CHECK: fmov d30, #16.00000000
|
|
0x2 0x10 0x28 0x1e
|
|
0x3 0x10 0x2e 0x1e
|
|
0x1e 0x10 0x66 0x1e
|
|
|
|
# CHECK: fmov s4, #1.06250000
|
|
# CHECK: fmov d10, #1.93750000
|
|
0x4 0x30 0x2e 0x1e
|
|
0xa 0xf0 0x6f 0x1e
|
|
|
|
# CHECK: fmov s12, #-1.00000000
|
|
0xc 0x10 0x3e 0x1e
|
|
|
|
# CHECK: fmov d16, #8.50000000
|
|
0x10 0x30 0x64 0x1e
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load-register (literal)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: ldr w3, #0
|
|
# CHECK: ldr x29, #4
|
|
# CHECK: ldrsw xzr, #-4
|
|
0x03 0x00 0x00 0x18
|
|
0x3d 0x00 0x00 0x58
|
|
0xff 0xff 0xff 0x98
|
|
|
|
# CHECK: ldr s0, #8
|
|
# CHECK: ldr d0, #1048572
|
|
# CHECK: ldr q0, #-1048576
|
|
0x40 0x00 0x00 0x1c
|
|
0xe0 0xff 0x7f 0x5c
|
|
0x00 0x00 0x80 0x9c
|
|
|
|
# CHECK: prfm pldl1strm, #0
|
|
# CHECK: prfm #22, #0
|
|
0x01 0x00 0x00 0xd8
|
|
0x16 0x00 0x00 0xd8
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load/store exclusive
|
|
#------------------------------------------------------------------------------
|
|
|
|
#CHECK: stxrb w18, w8, [sp]
|
|
#CHECK: stxrh w24, w15, [x16]
|
|
#CHECK: stxr w5, w6, [x17]
|
|
#CHECK: stxr w1, x10, [x21]
|
|
#CHECK: stxr w1, x10, [x21]
|
|
0xe8 0x7f 0x12 0x08
|
|
0x0f 0x7e 0x18 0x48
|
|
0x26 0x7e 0x05 0x88
|
|
0xaa 0x7e 0x01 0xc8
|
|
0xaa 0x7a 0x01 0xc8
|
|
|
|
#CHECK: ldxrb w30, [x0]
|
|
#CHECK: ldxrh w17, [x4]
|
|
#CHECK: ldxr w22, [sp]
|
|
#CHECK: ldxr x11, [x29]
|
|
#CHECK: ldxr x11, [x29]
|
|
#CHECK: ldxr x11, [x29]
|
|
0x1e 0x7c 0x5f 0x08
|
|
0x91 0x7c 0x5f 0x48
|
|
0xf6 0x7f 0x5f 0x88
|
|
0xab 0x7f 0x5f 0xc8
|
|
0xab 0x6f 0x5f 0xc8
|
|
0xab 0x7f 0x5e 0xc8
|
|
|
|
#CHECK: stxp w12, w11, w10, [sp]
|
|
#CHECK: stxp wzr, x27, x9, [x12]
|
|
0xeb 0x2b 0x2c 0x88
|
|
0x9b 0x25 0x3f 0xc8
|
|
|
|
#CHECK: ldxp w0, wzr, [sp]
|
|
#CHECK: ldxp x17, x0, [x18]
|
|
#CHECK: ldxp x17, x0, [x18]
|
|
0xe0 0x7f 0x7f 0x88
|
|
0x51 0x02 0x7f 0xc8
|
|
0x51 0x02 0x7e 0xc8
|
|
|
|
#CHECK: stlxrb w12, w22, [x0]
|
|
#CHECK: stlxrh w10, w1, [x1]
|
|
#CHECK: stlxr w9, w2, [x2]
|
|
#CHECK: stlxr w9, x3, [sp]
|
|
|
|
0x16 0xfc 0x0c 0x08
|
|
0x21 0xfc 0x0a 0x48
|
|
0x42 0xfc 0x09 0x88
|
|
0xe3 0xff 0x09 0xc8
|
|
|
|
#CHECK: ldaxrb w8, [x4]
|
|
#CHECK: ldaxrh w7, [x5]
|
|
#CHECK: ldaxr w6, [sp]
|
|
#CHECK: ldaxr x5, [x6]
|
|
#CHECK: ldaxr x5, [x6]
|
|
#CHECK: ldaxr x5, [x6]
|
|
0x88 0xfc 0x5f 0x08
|
|
0xa7 0xfc 0x5f 0x48
|
|
0xe6 0xff 0x5f 0x88
|
|
0xc5 0xfc 0x5f 0xc8
|
|
0xc5 0xec 0x5f 0xc8
|
|
0xc5 0xfc 0x5e 0xc8
|
|
|
|
#CHECK: stlxp w4, w5, w6, [sp]
|
|
#CHECK: stlxp wzr, x6, x7, [x1]
|
|
0xe5 0x9b 0x24 0x88
|
|
0x26 0x9c 0x3f 0xc8
|
|
|
|
#CHECK: ldaxp w5, w18, [sp]
|
|
#CHECK: ldaxp x6, x19, [x22]
|
|
#CHECK: ldaxp x6, x19, [x22]
|
|
0xe5 0xcb 0x7f 0x88
|
|
0xc6 0xce 0x7f 0xc8
|
|
0xc6 0xce 0x7e 0xc8
|
|
|
|
#CHECK: stlrb w24, [sp]
|
|
#CHECK: stlrh w25, [x30]
|
|
#CHECK: stlr w26, [x29]
|
|
#CHECK: stlr x27, [x28]
|
|
#CHECK: stlr x27, [x28]
|
|
#CHECK: stlr x27, [x28]
|
|
0xf8 0xff 0x9f 0x08
|
|
0xd9 0xff 0x9f 0x48
|
|
0xba 0xff 0x9f 0x88
|
|
0x9b 0xff 0x9f 0xc8
|
|
0x9b 0xef 0x9f 0xc8
|
|
0x9b 0xff 0x9e 0xc8
|
|
|
|
#CHECK: ldarb w23, [sp]
|
|
#CHECK: ldarh w22, [x30]
|
|
#CHECK: ldar wzr, [x29]
|
|
#CHECK: ldar x21, [x28]
|
|
#CHECK: ldar x21, [x28]
|
|
#CHECK: ldar x21, [x28]
|
|
0xf7 0xff 0xdf 0x08
|
|
0xd6 0xff 0xdf 0x48
|
|
0xbf 0xff 0xdf 0x88
|
|
0x95 0xff 0xdf 0xc8
|
|
0x95 0xef 0xdf 0xc8
|
|
0x95 0xff 0xde 0xc8
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load/store (unscaled immediate)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: sturb w9, [sp]
|
|
# CHECK: sturh wzr, [x12, #255]
|
|
# CHECK: stur w16, [x0, #-256]
|
|
# CHECK: stur x28, [x14, #1]
|
|
0xe9 0x3 0x0 0x38
|
|
0x9f 0xf1 0xf 0x78
|
|
0x10 0x0 0x10 0xb8
|
|
0xdc 0x11 0x0 0xf8
|
|
|
|
# CHECK: ldurb w1, [x20, #255]
|
|
# CHECK: ldurh w20, [x1, #255]
|
|
# CHECK: ldur w12, [sp, #255]
|
|
# CHECK: ldur xzr, [x12, #255]
|
|
0x81 0xf2 0x4f 0x38
|
|
0x34 0xf0 0x4f 0x78
|
|
0xec 0xf3 0x4f 0xb8
|
|
0x9f 0xf1 0x4f 0xf8
|
|
|
|
# CHECK: ldursb x9, [x7, #-256]
|
|
# CHECK: ldursh x17, [x19, #-256]
|
|
# CHECK: ldursw x20, [x15, #-256]
|
|
# CHECK: prfum pldl2keep, [sp, #-256]
|
|
# CHECK: ldursb w19, [x1, #-256]
|
|
# CHECK: ldursh w15, [x21, #-256]
|
|
0xe9 0x0 0x90 0x38
|
|
0x71 0x2 0x90 0x78
|
|
0xf4 0x1 0x90 0xb8
|
|
0xe2 0x3 0x90 0xf8
|
|
0x33 0x0 0xd0 0x38
|
|
0xaf 0x2 0xd0 0x78
|
|
|
|
# CHECK: stur b0, [sp, #1]
|
|
# CHECK: stur h12, [x12, #-1]
|
|
# CHECK: stur s15, [x0, #255]
|
|
# CHECK: stur d31, [x5, #25]
|
|
# CHECK: stur q9, [x5]
|
|
0xe0 0x13 0x0 0x3c
|
|
0x8c 0xf1 0x1f 0x7c
|
|
0xf 0xf0 0xf 0xbc
|
|
0xbf 0x90 0x1 0xfc
|
|
0xa9 0x0 0x80 0x3c
|
|
|
|
# CHECK: ldur b3, [sp]
|
|
# CHECK: ldur h5, [x4, #-256]
|
|
# CHECK: ldur s7, [x12, #-1]
|
|
# CHECK: ldur d11, [x19, #4]
|
|
# CHECK: ldur q13, [x1, #2]
|
|
0xe3 0x3 0x40 0x3c
|
|
0x85 0x0 0x50 0x7c
|
|
0x87 0xf1 0x5f 0xbc
|
|
0x6b 0x42 0x40 0xfc
|
|
0x2d 0x20 0xc0 0x3c
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load/store (immediate post-indexed)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# E.g. "str xzr, [sp], #4" is *not* unpredictable
|
|
# CHECK-NOT: warning: potentially undefined instruction encoding
|
|
0xff 0x47 0x40 0xb8
|
|
|
|
# CHECK: strb w9, [x2], #255
|
|
# CHECK: strb w10, [x3], #1
|
|
# CHECK: strb w10, [x3], #-256
|
|
# CHECK: strh w9, [x2], #255
|
|
# CHECK: strh w9, [x2], #1
|
|
# CHECK: strh w10, [x3], #-256
|
|
0x49 0xf4 0xf 0x38
|
|
0x6a 0x14 0x0 0x38
|
|
0x6a 0x4 0x10 0x38
|
|
0x49 0xf4 0xf 0x78
|
|
0x49 0x14 0x0 0x78
|
|
0x6a 0x4 0x10 0x78
|
|
|
|
# CHECK: str w19, [sp], #255
|
|
# CHECK: str w20, [x30], #1
|
|
# CHECK: str w21, [x12], #-256
|
|
# CHECK: str xzr, [x9], #255
|
|
# CHECK: str x2, [x3], #1
|
|
# CHECK: str x19, [x12], #-256
|
|
0xf3 0xf7 0xf 0xb8
|
|
0xd4 0x17 0x0 0xb8
|
|
0x95 0x5 0x10 0xb8
|
|
0x3f 0xf5 0xf 0xf8
|
|
0x62 0x14 0x0 0xf8
|
|
0x93 0x5 0x10 0xf8
|
|
|
|
# CHECK: ldrb w9, [x2], #255
|
|
# CHECK: ldrb w10, [x3], #1
|
|
# CHECK: ldrb w10, [x3], #-256
|
|
# CHECK: ldrh w9, [x2], #255
|
|
# CHECK: ldrh w9, [x2], #1
|
|
# CHECK: ldrh w10, [x3], #-256
|
|
0x49 0xf4 0x4f 0x38
|
|
0x6a 0x14 0x40 0x38
|
|
0x6a 0x4 0x50 0x38
|
|
0x49 0xf4 0x4f 0x78
|
|
0x49 0x14 0x40 0x78
|
|
0x6a 0x4 0x50 0x78
|
|
|
|
# CHECK: ldr w19, [sp], #255
|
|
# CHECK: ldr w20, [x30], #1
|
|
# CHECK: ldr w21, [x12], #-256
|
|
# CHECK: ldr xzr, [x9], #255
|
|
# CHECK: ldr x2, [x3], #1
|
|
# CHECK: ldr x19, [x12], #-256
|
|
0xf3 0xf7 0x4f 0xb8
|
|
0xd4 0x17 0x40 0xb8
|
|
0x95 0x5 0x50 0xb8
|
|
0x3f 0xf5 0x4f 0xf8
|
|
0x62 0x14 0x40 0xf8
|
|
0x93 0x5 0x50 0xf8
|
|
|
|
# CHECK: ldrsb xzr, [x9], #255
|
|
# CHECK: ldrsb x2, [x3], #1
|
|
# CHECK: ldrsb x19, [x12], #-256
|
|
# CHECK: ldrsh xzr, [x9], #255
|
|
# CHECK: ldrsh x2, [x3], #1
|
|
# CHECK: ldrsh x19, [x12], #-256
|
|
# CHECK: ldrsw xzr, [x9], #255
|
|
# CHECK: ldrsw x2, [x3], #1
|
|
# CHECK: ldrsw x19, [x12], #-256
|
|
0x3f 0xf5 0x8f 0x38
|
|
0x62 0x14 0x80 0x38
|
|
0x93 0x5 0x90 0x38
|
|
0x3f 0xf5 0x8f 0x78
|
|
0x62 0x14 0x80 0x78
|
|
0x93 0x5 0x90 0x78
|
|
0x3f 0xf5 0x8f 0xb8
|
|
0x62 0x14 0x80 0xb8
|
|
0x93 0x5 0x90 0xb8
|
|
|
|
# CHECK: ldrsb wzr, [x9], #255
|
|
# CHECK: ldrsb w2, [x3], #1
|
|
# CHECK: ldrsb w19, [x12], #-256
|
|
# CHECK: ldrsh wzr, [x9], #255
|
|
# CHECK: ldrsh w2, [x3], #1
|
|
# CHECK: ldrsh w19, [x12], #-256
|
|
0x3f 0xf5 0xcf 0x38
|
|
0x62 0x14 0xc0 0x38
|
|
0x93 0x5 0xd0 0x38
|
|
0x3f 0xf5 0xcf 0x78
|
|
0x62 0x14 0xc0 0x78
|
|
0x93 0x5 0xd0 0x78
|
|
|
|
# CHECK: str b0, [x0], #255
|
|
# CHECK: str b3, [x3], #1
|
|
# CHECK: str b5, [sp], #-256
|
|
# CHECK: str h10, [x10], #255
|
|
# CHECK: str h13, [x23], #1
|
|
# CHECK: str h15, [sp], #-256
|
|
# CHECK: str s20, [x20], #255
|
|
# CHECK: str s23, [x23], #1
|
|
# CHECK: str s25, [x0], #-256
|
|
# CHECK: str d20, [x20], #255
|
|
# CHECK: str d23, [x23], #1
|
|
# CHECK: str d25, [x0], #-256
|
|
0x0 0xf4 0xf 0x3c
|
|
0x63 0x14 0x0 0x3c
|
|
0xe5 0x7 0x10 0x3c
|
|
0x4a 0xf5 0xf 0x7c
|
|
0xed 0x16 0x0 0x7c
|
|
0xef 0x7 0x10 0x7c
|
|
0x94 0xf6 0xf 0xbc
|
|
0xf7 0x16 0x0 0xbc
|
|
0x19 0x4 0x10 0xbc
|
|
0x94 0xf6 0xf 0xfc
|
|
0xf7 0x16 0x0 0xfc
|
|
0x19 0x4 0x10 0xfc
|
|
|
|
# CHECK: ldr b0, [x0], #255
|
|
# CHECK: ldr b3, [x3], #1
|
|
# CHECK: ldr b5, [sp], #-256
|
|
# CHECK: ldr h10, [x10], #255
|
|
# CHECK: ldr h13, [x23], #1
|
|
# CHECK: ldr h15, [sp], #-256
|
|
# CHECK: ldr s20, [x20], #255
|
|
# CHECK: ldr s23, [x23], #1
|
|
# CHECK: ldr s25, [x0], #-256
|
|
# CHECK: ldr d20, [x20], #255
|
|
# CHECK: ldr d23, [x23], #1
|
|
# CHECK: ldr d25, [x0], #-256
|
|
0x0 0xf4 0x4f 0x3c
|
|
0x63 0x14 0x40 0x3c
|
|
0xe5 0x7 0x50 0x3c
|
|
0x4a 0xf5 0x4f 0x7c
|
|
0xed 0x16 0x40 0x7c
|
|
0xef 0x7 0x50 0x7c
|
|
0x94 0xf6 0x4f 0xbc
|
|
0xf7 0x16 0x40 0xbc
|
|
0x19 0x4 0x50 0xbc
|
|
0x94 0xf6 0x4f 0xfc
|
|
0xf7 0x16 0x40 0xfc
|
|
0x19 0x4 0x50 0xfc
|
|
0x34 0xf4 0xcf 0x3c
|
|
|
|
# CHECK: ldr q20, [x1], #255
|
|
# CHECK: ldr q23, [x9], #1
|
|
# CHECK: ldr q25, [x20], #-256
|
|
# CHECK: str q10, [x1], #255
|
|
# CHECK: str q22, [sp], #1
|
|
# CHECK: str q21, [x20], #-256
|
|
0x37 0x15 0xc0 0x3c
|
|
0x99 0x6 0xd0 0x3c
|
|
0x2a 0xf4 0x8f 0x3c
|
|
0xf6 0x17 0x80 0x3c
|
|
0x95 0x6 0x90 0x3c
|
|
|
|
#-------------------------------------------------------------------------------
|
|
# Load-store register (immediate pre-indexed)
|
|
#-------------------------------------------------------------------------------
|
|
|
|
# E.g. "str xzr, [sp, #4]!" is *not* unpredictable
|
|
# CHECK-NOT: warning: potentially undefined instruction encoding
|
|
0xff 0xf 0x40 0xf8
|
|
|
|
# CHECK: ldr x3, [x4, #0]!
|
|
0x83 0xc 0x40 0xf8
|
|
|
|
# CHECK: strb w9, [x2, #255]!
|
|
# CHECK: strb w10, [x3, #1]!
|
|
# CHECK: strb w10, [x3, #-256]!
|
|
# CHECK: strh w9, [x2, #255]!
|
|
# CHECK: strh w9, [x2, #1]!
|
|
# CHECK: strh w10, [x3, #-256]!
|
|
0x49 0xfc 0xf 0x38
|
|
0x6a 0x1c 0x0 0x38
|
|
0x6a 0xc 0x10 0x38
|
|
0x49 0xfc 0xf 0x78
|
|
0x49 0x1c 0x0 0x78
|
|
0x6a 0xc 0x10 0x78
|
|
|
|
# CHECK: str w19, [sp, #255]!
|
|
# CHECK: str w20, [x30, #1]!
|
|
# CHECK: str w21, [x12, #-256]!
|
|
# CHECK: str xzr, [x9, #255]!
|
|
# CHECK: str x2, [x3, #1]!
|
|
# CHECK: str x19, [x12, #-256]!
|
|
0xf3 0xff 0xf 0xb8
|
|
0xd4 0x1f 0x0 0xb8
|
|
0x95 0xd 0x10 0xb8
|
|
0x3f 0xfd 0xf 0xf8
|
|
0x62 0x1c 0x0 0xf8
|
|
0x93 0xd 0x10 0xf8
|
|
|
|
# CHECK: ldrb w9, [x2, #255]!
|
|
# CHECK: ldrb w10, [x3, #1]!
|
|
# CHECK: ldrb w10, [x3, #-256]!
|
|
# CHECK: ldrh w9, [x2, #255]!
|
|
# CHECK: ldrh w9, [x2, #1]!
|
|
# CHECK: ldrh w10, [x3, #-256]!
|
|
0x49 0xfc 0x4f 0x38
|
|
0x6a 0x1c 0x40 0x38
|
|
0x6a 0xc 0x50 0x38
|
|
0x49 0xfc 0x4f 0x78
|
|
0x49 0x1c 0x40 0x78
|
|
0x6a 0xc 0x50 0x78
|
|
|
|
# CHECK: ldr w19, [sp, #255]!
|
|
# CHECK: ldr w20, [x30, #1]!
|
|
# CHECK: ldr w21, [x12, #-256]!
|
|
# CHECK: ldr xzr, [x9, #255]!
|
|
# CHECK: ldr x2, [x3, #1]!
|
|
# CHECK: ldr x19, [x12, #-256]!
|
|
0xf3 0xff 0x4f 0xb8
|
|
0xd4 0x1f 0x40 0xb8
|
|
0x95 0xd 0x50 0xb8
|
|
0x3f 0xfd 0x4f 0xf8
|
|
0x62 0x1c 0x40 0xf8
|
|
0x93 0xd 0x50 0xf8
|
|
|
|
# CHECK: ldrsb xzr, [x9, #255]!
|
|
# CHECK: ldrsb x2, [x3, #1]!
|
|
# CHECK: ldrsb x19, [x12, #-256]!
|
|
# CHECK: ldrsh xzr, [x9, #255]!
|
|
# CHECK: ldrsh x2, [x3, #1]!
|
|
# CHECK: ldrsh x19, [x12, #-256]!
|
|
# CHECK: ldrsw xzr, [x9, #255]!
|
|
# CHECK: ldrsw x2, [x3, #1]!
|
|
# CHECK: ldrsw x19, [x12, #-256]!
|
|
0x3f 0xfd 0x8f 0x38
|
|
0x62 0x1c 0x80 0x38
|
|
0x93 0xd 0x90 0x38
|
|
0x3f 0xfd 0x8f 0x78
|
|
0x62 0x1c 0x80 0x78
|
|
0x93 0xd 0x90 0x78
|
|
0x3f 0xfd 0x8f 0xb8
|
|
0x62 0x1c 0x80 0xb8
|
|
0x93 0xd 0x90 0xb8
|
|
|
|
# CHECK: ldrsb wzr, [x9, #255]!
|
|
# CHECK: ldrsb w2, [x3, #1]!
|
|
# CHECK: ldrsb w19, [x12, #-256]!
|
|
# CHECK: ldrsh wzr, [x9, #255]!
|
|
# CHECK: ldrsh w2, [x3, #1]!
|
|
# CHECK: ldrsh w19, [x12, #-256]!
|
|
0x3f 0xfd 0xcf 0x38
|
|
0x62 0x1c 0xc0 0x38
|
|
0x93 0xd 0xd0 0x38
|
|
0x3f 0xfd 0xcf 0x78
|
|
0x62 0x1c 0xc0 0x78
|
|
0x93 0xd 0xd0 0x78
|
|
|
|
# CHECK: str b0, [x0, #255]!
|
|
# CHECK: str b3, [x3, #1]!
|
|
# CHECK: str b5, [sp, #-256]!
|
|
# CHECK: str h10, [x10, #255]!
|
|
# CHECK: str h13, [x23, #1]!
|
|
# CHECK: str h15, [sp, #-256]!
|
|
# CHECK: str s20, [x20, #255]!
|
|
# CHECK: str s23, [x23, #1]!
|
|
# CHECK: str s25, [x0, #-256]!
|
|
# CHECK: str d20, [x20, #255]!
|
|
# CHECK: str d23, [x23, #1]!
|
|
# CHECK: str d25, [x0, #-256]!
|
|
0x0 0xfc 0xf 0x3c
|
|
0x63 0x1c 0x0 0x3c
|
|
0xe5 0xf 0x10 0x3c
|
|
0x4a 0xfd 0xf 0x7c
|
|
0xed 0x1e 0x0 0x7c
|
|
0xef 0xf 0x10 0x7c
|
|
0x94 0xfe 0xf 0xbc
|
|
0xf7 0x1e 0x0 0xbc
|
|
0x19 0xc 0x10 0xbc
|
|
0x94 0xfe 0xf 0xfc
|
|
0xf7 0x1e 0x0 0xfc
|
|
0x19 0xc 0x10 0xfc
|
|
|
|
# CHECK: ldr b0, [x0, #255]!
|
|
# CHECK: ldr b3, [x3, #1]!
|
|
# CHECK: ldr b5, [sp, #-256]!
|
|
# CHECK: ldr h10, [x10, #255]!
|
|
# CHECK: ldr h13, [x23, #1]!
|
|
# CHECK: ldr h15, [sp, #-256]!
|
|
# CHECK: ldr s20, [x20, #255]!
|
|
# CHECK: ldr s23, [x23, #1]!
|
|
# CHECK: ldr s25, [x0, #-256]!
|
|
# CHECK: ldr d20, [x20, #255]!
|
|
# CHECK: ldr d23, [x23, #1]!
|
|
# CHECK: ldr d25, [x0, #-256]!
|
|
0x0 0xfc 0x4f 0x3c
|
|
0x63 0x1c 0x40 0x3c
|
|
0xe5 0xf 0x50 0x3c
|
|
0x4a 0xfd 0x4f 0x7c
|
|
0xed 0x1e 0x40 0x7c
|
|
0xef 0xf 0x50 0x7c
|
|
0x94 0xfe 0x4f 0xbc
|
|
0xf7 0x1e 0x40 0xbc
|
|
0x19 0xc 0x50 0xbc
|
|
0x94 0xfe 0x4f 0xfc
|
|
0xf7 0x1e 0x40 0xfc
|
|
0x19 0xc 0x50 0xfc
|
|
|
|
# CHECK: ldr q20, [x1, #255]!
|
|
# CHECK: ldr q23, [x9, #1]!
|
|
# CHECK: ldr q25, [x20, #-256]!
|
|
# CHECK: str q10, [x1, #255]!
|
|
# CHECK: str q22, [sp, #1]!
|
|
# CHECK: str q21, [x20, #-256]!
|
|
0x34 0xfc 0xcf 0x3c
|
|
0x37 0x1d 0xc0 0x3c
|
|
0x99 0xe 0xd0 0x3c
|
|
0x2a 0xfc 0x8f 0x3c
|
|
0xf6 0x1f 0x80 0x3c
|
|
0x95 0xe 0x90 0x3c
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load/store (unprivileged)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: sttrb w9, [sp]
|
|
# CHECK: sttrh wzr, [x12, #255]
|
|
# CHECK: sttr w16, [x0, #-256]
|
|
# CHECK: sttr x28, [x14, #1]
|
|
0xe9 0x0b 0x0 0x38
|
|
0x9f 0xf9 0xf 0x78
|
|
0x10 0x08 0x10 0xb8
|
|
0xdc 0x19 0x0 0xf8
|
|
|
|
# CHECK: ldtrb w1, [x20, #255]
|
|
# CHECK: ldtrh w20, [x1, #255]
|
|
# CHECK: ldtr w12, [sp, #255]
|
|
# CHECK: ldtr xzr, [x12, #255]
|
|
0x81 0xfa 0x4f 0x38
|
|
0x34 0xf8 0x4f 0x78
|
|
0xec 0xfb 0x4f 0xb8
|
|
0x9f 0xf9 0x4f 0xf8
|
|
|
|
# CHECK: ldtrsb x9, [x7, #-256]
|
|
# CHECK: ldtrsh x17, [x19, #-256]
|
|
# CHECK: ldtrsw x20, [x15, #-256]
|
|
# CHECK: ldtrsb w19, [x1, #-256]
|
|
# CHECK: ldtrsh w15, [x21, #-256]
|
|
0xe9 0x08 0x90 0x38
|
|
0x71 0x0a 0x90 0x78
|
|
0xf4 0x09 0x90 0xb8
|
|
0x33 0x08 0xd0 0x38
|
|
0xaf 0x0a 0xd0 0x78
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load/store (unsigned immediate)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: ldr x0, [x0]
|
|
# CHECK: ldr x4, [x29]
|
|
# CHECK: ldr x30, [x12, #32760]
|
|
# CHECK: ldr x20, [sp, #8]
|
|
0x0 0x0 0x40 0xf9
|
|
0xa4 0x3 0x40 0xf9
|
|
0x9e 0xfd 0x7f 0xf9
|
|
0xf4 0x7 0x40 0xf9
|
|
|
|
# CHECK: ldr xzr, [sp]
|
|
0xff 0x3 0x40 0xf9
|
|
|
|
# CHECK: ldr w2, [sp]
|
|
# CHECK: ldr w17, [sp, #16380]
|
|
# CHECK: ldr w13, [x2, #4]
|
|
0xe2 0x3 0x40 0xb9
|
|
0xf1 0xff 0x7f 0xb9
|
|
0x4d 0x4 0x40 0xb9
|
|
|
|
# CHECK: ldrsw x2, [x5, #4]
|
|
# CHECK: ldrsw x23, [sp, #16380]
|
|
0xa2 0x4 0x80 0xb9
|
|
0xf7 0xff 0xbf 0xb9
|
|
|
|
# CHECK: ldrh w2, [x4]
|
|
# CHECK: ldrsh w23, [x6, #8190]
|
|
# CHECK: ldrsh wzr, [sp, #2]
|
|
# CHECK: ldrsh x29, [x2, #2]
|
|
0x82 0x0 0x40 0x79
|
|
0xd7 0xfc 0xff 0x79
|
|
0xff 0x7 0xc0 0x79
|
|
0x5d 0x4 0x80 0x79
|
|
|
|
# CHECK: ldrb w26, [x3, #121]
|
|
# CHECK: ldrb w12, [x2]
|
|
# CHECK: ldrsb w27, [sp, #4095]
|
|
# CHECK: ldrsb xzr, [x15]
|
|
0x7a 0xe4 0x41 0x39
|
|
0x4c 0x0 0x40 0x39
|
|
0xfb 0xff 0xff 0x39
|
|
0xff 0x1 0x80 0x39
|
|
|
|
# CHECK: str x30, [sp]
|
|
# CHECK: str w20, [x4, #16380]
|
|
# CHECK: strh w20, [x10, #14]
|
|
# CHECK: strh w17, [sp, #8190]
|
|
# CHECK: strb w23, [x3, #4095]
|
|
# CHECK: strb wzr, [x2]
|
|
0xfe 0x3 0x0 0xf9
|
|
0x94 0xfc 0x3f 0xb9
|
|
0x54 0x1d 0x0 0x79
|
|
0xf1 0xff 0x3f 0x79
|
|
0x77 0xfc 0x3f 0x39
|
|
0x5f 0x0 0x0 0x39
|
|
|
|
# CHECK: ldr b31, [sp, #4095]
|
|
# CHECK: ldr h20, [x2, #8190]
|
|
# CHECK: ldr s10, [x19, #16380]
|
|
# CHECK: ldr d3, [x10, #32760]
|
|
# CHECK: str q12, [sp, #65520]
|
|
0xff 0xff 0x7f 0x3d
|
|
0x54 0xfc 0x7f 0x7d
|
|
0x6a 0xfe 0x7f 0xbd
|
|
0x43 0xfd 0x7f 0xfd
|
|
0xec 0xff 0xbf 0x3d
|
|
|
|
# CHECK: prfm pldl1keep, [sp, #8]
|
|
# CHECK: prfm pldl1strm, [x3{{(, #0)?}}]
|
|
# CHECK: prfm pldl2keep, [x5, #16]
|
|
# CHECK: prfm pldl2strm, [x2{{(, #0)?}}]
|
|
# CHECK: prfm pldl3keep, [x5{{(, #0)?}}]
|
|
# CHECK: prfm pldl3strm, [x6{{(, #0)?}}]
|
|
# CHECK: prfm plil1keep, [sp, #8]
|
|
# CHECK: prfm plil1strm, [x3{{(, #0)?}}]
|
|
# CHECK: prfm plil2keep, [x5, #16]
|
|
# CHECK: prfm plil2strm, [x2{{(, #0)?}}]
|
|
# CHECK: prfm plil3keep, [x5{{(, #0)?}}]
|
|
# CHECK: prfm plil3strm, [x6{{(, #0)?}}]
|
|
# CHECK: prfm pstl1keep, [sp, #8]
|
|
# CHECK: prfm pstl1strm, [x3{{(, #0)?}}]
|
|
# CHECK: prfm pstl2keep, [x5, #16]
|
|
# CHECK: prfm pstl2strm, [x2{{(, #0)?}}]
|
|
# CHECK: prfm pstl3keep, [x5{{(, #0)?}}]
|
|
# CHECK: prfm pstl3strm, [x6{{(, #0)?}}]
|
|
0xe0 0x07 0x80 0xf9
|
|
0x61 0x00 0x80 0xf9
|
|
0xa2 0x08 0x80 0xf9
|
|
0x43 0x00 0x80 0xf9
|
|
0xa4 0x00 0x80 0xf9
|
|
0xc5 0x00 0x80 0xf9
|
|
0xe8 0x07 0x80 0xf9
|
|
0x69 0x00 0x80 0xf9
|
|
0xaa 0x08 0x80 0xf9
|
|
0x4b 0x00 0x80 0xf9
|
|
0xac 0x00 0x80 0xf9
|
|
0xcd 0x00 0x80 0xf9
|
|
0xf0 0x07 0x80 0xf9
|
|
0x71 0x00 0x80 0xf9
|
|
0xb2 0x08 0x80 0xf9
|
|
0x53 0x00 0x80 0xf9
|
|
0xb4 0x00 0x80 0xf9
|
|
0xd5 0x00 0x80 0xf9
|
|
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load/store (register offset)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: ldrb w3, [sp, x5]
|
|
# CHECK: ldrb w9, [x27, x6]
|
|
# CHECK: ldrsb w10, [x30, x7]
|
|
# CHECK: ldrb w11, [x29, x3, sxtx]
|
|
# CHECK: strb w12, [x28, xzr, sxtx]
|
|
# CHECK: ldrb w14, [x26, w6, uxtw]
|
|
# CHECK: ldrsb w15, [x25, w7, uxtw]
|
|
# CHECK: ldrb w17, [x23, w9, sxtw]
|
|
# CHECK: ldrsb x18, [x22, w10, sxtw]
|
|
0xe3 0x6b 0x65 0x38
|
|
0x69 0x6b 0x66 0x38
|
|
0xca 0x6b 0xe7 0x38
|
|
0xab 0xeb 0x63 0x38
|
|
0x8c 0xeb 0x3f 0x38
|
|
0x4e 0x4b 0x66 0x38
|
|
0x2f 0x4b 0xe7 0x38
|
|
0xf1 0xca 0x69 0x38
|
|
0xd2 0xca 0xaa 0x38
|
|
|
|
# CHECK: ldrsh w3, [sp, x5]
|
|
# CHECK: ldrsh w9, [x27, x6]
|
|
# CHECK: ldrh w10, [x30, x7, lsl #1]
|
|
# CHECK: strh w11, [x29, x3, sxtx]
|
|
# CHECK: ldrh w12, [x28, xzr, sxtx]
|
|
# CHECK: ldrsh x13, [x27, x5, sxtx #1]
|
|
# CHECK: ldrh w14, [x26, w6, uxtw]
|
|
# CHECK: ldrh w15, [x25, w7, uxtw]
|
|
# CHECK: ldrsh w16, [x24, w8, uxtw #1]
|
|
# CHECK: ldrh w17, [x23, w9, sxtw]
|
|
# CHECK: ldrh w18, [x22, w10, sxtw]
|
|
# CHECK: strh w19, [x21, wzr, sxtw #1]
|
|
0xe3 0x6b 0xe5 0x78
|
|
0x69 0x6b 0xe6 0x78
|
|
0xca 0x7b 0x67 0x78
|
|
0xab 0xeb 0x23 0x78
|
|
0x8c 0xeb 0x7f 0x78
|
|
0x6d 0xfb 0xa5 0x78
|
|
0x4e 0x4b 0x66 0x78
|
|
0x2f 0x4b 0x67 0x78
|
|
0x10 0x5b 0xe8 0x78
|
|
0xf1 0xca 0x69 0x78
|
|
0xd2 0xca 0x6a 0x78
|
|
0xb3 0xda 0x3f 0x78
|
|
|
|
# CHECK: ldr w3, [sp, x5]
|
|
# CHECK: ldr s9, [x27, x6]
|
|
# CHECK: ldr w10, [x30, x7, lsl #2]
|
|
# CHECK: ldr w11, [x29, x3, sxtx]
|
|
# CHECK: str s12, [x28, xzr, sxtx]
|
|
# CHECK: str w13, [x27, x5, sxtx #2]
|
|
# CHECK: str w14, [x26, w6, uxtw]
|
|
# CHECK: ldr w15, [x25, w7, uxtw]
|
|
# CHECK: ldr w16, [x24, w8, uxtw #2]
|
|
# CHECK: ldrsw x17, [x23, w9, sxtw]
|
|
# CHECK: ldr w18, [x22, w10, sxtw]
|
|
# CHECK: ldrsw x19, [x21, wzr, sxtw #2]
|
|
0xe3 0x6b 0x65 0xb8
|
|
0x69 0x6b 0x66 0xbc
|
|
0xca 0x7b 0x67 0xb8
|
|
0xab 0xeb 0x63 0xb8
|
|
0x8c 0xeb 0x3f 0xbc
|
|
0x6d 0xfb 0x25 0xb8
|
|
0x4e 0x4b 0x26 0xb8
|
|
0x2f 0x4b 0x67 0xb8
|
|
0x10 0x5b 0x68 0xb8
|
|
0xf1 0xca 0xa9 0xb8
|
|
0xd2 0xca 0x6a 0xb8
|
|
0xb3 0xda 0xbf 0xb8
|
|
|
|
# CHECK: ldr x3, [sp, x5]
|
|
# CHECK: str x9, [x27, x6]
|
|
# CHECK: ldr d10, [x30, x7, lsl #3]
|
|
# CHECK: str x11, [x29, x3, sxtx]
|
|
# CHECK: ldr x12, [x28, xzr, sxtx]
|
|
# CHECK: ldr x13, [x27, x5, sxtx #3]
|
|
# CHECK: prfm pldl1keep, [x26, w6, uxtw]
|
|
# CHECK: ldr x15, [x25, w7, uxtw]
|
|
# CHECK: ldr x16, [x24, w8, uxtw #3]
|
|
# CHECK: ldr x17, [x23, w9, sxtw]
|
|
# CHECK: ldr x18, [x22, w10, sxtw]
|
|
# CHECK: str d19, [x21, wzr, sxtw #3]
|
|
0xe3 0x6b 0x65 0xf8
|
|
0x69 0x6b 0x26 0xf8
|
|
0xca 0x7b 0x67 0xfc
|
|
0xab 0xeb 0x23 0xf8
|
|
0x8c 0xeb 0x7f 0xf8
|
|
0x6d 0xfb 0x65 0xf8
|
|
0x40 0x4b 0xa6 0xf8
|
|
0x2f 0x4b 0x67 0xf8
|
|
0x10 0x5b 0x68 0xf8
|
|
0xf1 0xca 0x69 0xf8
|
|
0xd2 0xca 0x6a 0xf8
|
|
0xb3 0xda 0x3f 0xfc
|
|
|
|
# CHECK: ldr q3, [sp, x5]
|
|
# CHECK: ldr q9, [x27, x6]
|
|
# CHECK: ldr q10, [x30, x7, lsl #4]
|
|
# CHECK: str q11, [x29, x3, sxtx]
|
|
# CHECK: str q12, [x28, xzr, sxtx]
|
|
# CHECK: str q13, [x27, x5, sxtx #4]
|
|
# CHECK: ldr q14, [x26, w6, uxtw]
|
|
# CHECK: ldr q15, [x25, w7, uxtw]
|
|
# CHECK: ldr q16, [x24, w8, uxtw #4]
|
|
# CHECK: ldr q17, [x23, w9, sxtw]
|
|
# CHECK: str q18, [x22, w10, sxtw]
|
|
# CHECK: ldr q19, [x21, wzr, sxtw #4]
|
|
0xe3 0x6b 0xe5 0x3c
|
|
0x69 0x6b 0xe6 0x3c
|
|
0xca 0x7b 0xe7 0x3c
|
|
0xab 0xeb 0xa3 0x3c
|
|
0x8c 0xeb 0xbf 0x3c
|
|
0x6d 0xfb 0xa5 0x3c
|
|
0x4e 0x4b 0xe6 0x3c
|
|
0x2f 0x4b 0xe7 0x3c
|
|
0x10 0x5b 0xe8 0x3c
|
|
0xf1 0xca 0xe9 0x3c
|
|
0xd2 0xca 0xaa 0x3c
|
|
0xb3 0xda 0xff 0x3c
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load/store register pair (offset)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: ldp w3, w5, [sp]
|
|
# CHECK: stp wzr, w9, [sp, #252]
|
|
# CHECK: ldp w2, wzr, [sp, #-256]
|
|
# CHECK: ldp w9, w10, [sp, #4]
|
|
0xe3 0x17 0x40 0x29
|
|
0xff 0xa7 0x1f 0x29
|
|
0xe2 0x7f 0x60 0x29
|
|
0xe9 0xab 0x40 0x29
|
|
|
|
# CHECK: ldpsw x9, x10, [sp, #4]
|
|
# CHECK: ldpsw x9, x10, [x2, #-256]
|
|
# CHECK: ldpsw x20, x30, [sp, #252]
|
|
0xe9 0xab 0x40 0x69
|
|
0x49 0x28 0x60 0x69
|
|
0xf4 0xfb 0x5f 0x69
|
|
|
|
# CHECK: ldp x21, x29, [x2, #504]
|
|
# CHECK: ldp x22, x23, [x3, #-512]
|
|
# CHECK: ldp x24, x25, [x4, #8]
|
|
0x55 0xf4 0x5f 0xa9
|
|
0x76 0x5c 0x60 0xa9
|
|
0x98 0xe4 0x40 0xa9
|
|
|
|
# CHECK: ldp s29, s28, [sp, #252]
|
|
# CHECK: stp s27, s26, [sp, #-256]
|
|
# CHECK: ldp s1, s2, [x3, #44]
|
|
0xfd 0xf3 0x5f 0x2d
|
|
0xfb 0x6b 0x20 0x2d
|
|
0x61 0x88 0x45 0x2d
|
|
|
|
# CHECK: stp d3, d5, [x9, #504]
|
|
# CHECK: stp d7, d11, [x10, #-512]
|
|
# CHECK: ldp d2, d3, [x30, #-8]
|
|
0x23 0x95 0x1f 0x6d
|
|
0x47 0x2d 0x20 0x6d
|
|
0xc2 0x8f 0x7f 0x6d
|
|
|
|
# CHECK: stp q3, q5, [sp]
|
|
# CHECK: stp q17, q19, [sp, #1008]
|
|
# CHECK: ldp q23, q29, [x1, #-1024]
|
|
0xe3 0x17 0x0 0xad
|
|
0xf1 0xcf 0x1f 0xad
|
|
0x37 0x74 0x60 0xad
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load/store register pair (post-indexed)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: ldp w3, w5, [sp], #0
|
|
# CHECK: stp wzr, w9, [sp], #252
|
|
# CHECK: ldp w2, wzr, [sp], #-256
|
|
# CHECK: ldp w9, w10, [sp], #4
|
|
0xe3 0x17 0xc0 0x28
|
|
0xff 0xa7 0x9f 0x28
|
|
0xe2 0x7f 0xe0 0x28
|
|
0xe9 0xab 0xc0 0x28
|
|
|
|
# CHECK: ldpsw x9, x10, [sp], #4
|
|
# CHECK: ldpsw x9, x10, [x2], #-256
|
|
# CHECK: ldpsw x20, x30, [sp], #252
|
|
0xe9 0xab 0xc0 0x68
|
|
0x49 0x28 0xe0 0x68
|
|
0xf4 0xfb 0xdf 0x68
|
|
|
|
# CHECK: ldp x21, x29, [x2], #504
|
|
# CHECK: ldp x22, x23, [x3], #-512
|
|
# CHECK: ldp x24, x25, [x4], #8
|
|
0x55 0xf4 0xdf 0xa8
|
|
0x76 0x5c 0xe0 0xa8
|
|
0x98 0xe4 0xc0 0xa8
|
|
|
|
# CHECK: ldp s29, s28, [sp], #252
|
|
# CHECK: stp s27, s26, [sp], #-256
|
|
# CHECK: ldp s1, s2, [x3], #44
|
|
0xfd 0xf3 0xdf 0x2c
|
|
0xfb 0x6b 0xa0 0x2c
|
|
0x61 0x88 0xc5 0x2c
|
|
|
|
# CHECK: stp d3, d5, [x9], #504
|
|
# CHECK: stp d7, d11, [x10], #-512
|
|
# CHECK: ldp d2, d3, [x30], #-8
|
|
0x23 0x95 0x9f 0x6c
|
|
0x47 0x2d 0xa0 0x6c
|
|
0xc2 0x8f 0xff 0x6c
|
|
|
|
# CHECK: stp q3, q5, [sp], #0
|
|
# CHECK: stp q17, q19, [sp], #1008
|
|
# CHECK: ldp q23, q29, [x1], #-1024
|
|
0xe3 0x17 0x80 0xac
|
|
0xf1 0xcf 0x9f 0xac
|
|
0x37 0x74 0xe0 0xac
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load/store register pair (pre-indexed)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: ldp w3, w5, [sp, #0]!
|
|
# CHECK: stp wzr, w9, [sp, #252]!
|
|
# CHECK: ldp w2, wzr, [sp, #-256]!
|
|
# CHECK: ldp w9, w10, [sp, #4]!
|
|
0xe3 0x17 0xc0 0x29
|
|
0xff 0xa7 0x9f 0x29
|
|
0xe2 0x7f 0xe0 0x29
|
|
0xe9 0xab 0xc0 0x29
|
|
|
|
# CHECK: ldpsw x9, x10, [sp, #4]!
|
|
# CHECK: ldpsw x9, x10, [x2, #-256]!
|
|
# CHECK: ldpsw x20, x30, [sp, #252]!
|
|
0xe9 0xab 0xc0 0x69
|
|
0x49 0x28 0xe0 0x69
|
|
0xf4 0xfb 0xdf 0x69
|
|
|
|
# CHECK: ldp x21, x29, [x2, #504]!
|
|
# CHECK: ldp x22, x23, [x3, #-512]!
|
|
# CHECK: ldp x24, x25, [x4, #8]!
|
|
0x55 0xf4 0xdf 0xa9
|
|
0x76 0x5c 0xe0 0xa9
|
|
0x98 0xe4 0xc0 0xa9
|
|
|
|
# CHECK: ldp s29, s28, [sp, #252]!
|
|
# CHECK: stp s27, s26, [sp, #-256]!
|
|
# CHECK: ldp s1, s2, [x3, #44]!
|
|
0xfd 0xf3 0xdf 0x2d
|
|
0xfb 0x6b 0xa0 0x2d
|
|
0x61 0x88 0xc5 0x2d
|
|
|
|
# CHECK: stp d3, d5, [x9, #504]!
|
|
# CHECK: stp d7, d11, [x10, #-512]!
|
|
# CHECK: ldp d2, d3, [x30, #-8]!
|
|
0x23 0x95 0x9f 0x6d
|
|
0x47 0x2d 0xa0 0x6d
|
|
0xc2 0x8f 0xff 0x6d
|
|
|
|
# CHECK: stp q3, q5, [sp, #0]!
|
|
# CHECK: stp q17, q19, [sp, #1008]!
|
|
# CHECK: ldp q23, q29, [x1, #-1024]!
|
|
0xe3 0x17 0x80 0xad
|
|
0xf1 0xcf 0x9f 0xad
|
|
0x37 0x74 0xe0 0xad
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load/store register pair (offset)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: ldnp w3, w5, [sp]
|
|
# CHECK: stnp wzr, w9, [sp, #252]
|
|
# CHECK: ldnp w2, wzr, [sp, #-256]
|
|
# CHECK: ldnp w9, w10, [sp, #4]
|
|
0xe3 0x17 0x40 0x28
|
|
0xff 0xa7 0x1f 0x28
|
|
0xe2 0x7f 0x60 0x28
|
|
0xe9 0xab 0x40 0x28
|
|
|
|
# CHECK: ldnp x21, x29, [x2, #504]
|
|
# CHECK: ldnp x22, x23, [x3, #-512]
|
|
# CHECK: ldnp x24, x25, [x4, #8]
|
|
0x55 0xf4 0x5f 0xa8
|
|
0x76 0x5c 0x60 0xa8
|
|
0x98 0xe4 0x40 0xa8
|
|
|
|
# CHECK: ldnp s29, s28, [sp, #252]
|
|
# CHECK: stnp s27, s26, [sp, #-256]
|
|
# CHECK: ldnp s1, s2, [x3, #44]
|
|
0xfd 0xf3 0x5f 0x2c
|
|
0xfb 0x6b 0x20 0x2c
|
|
0x61 0x88 0x45 0x2c
|
|
|
|
# CHECK: stnp d3, d5, [x9, #504]
|
|
# CHECK: stnp d7, d11, [x10, #-512]
|
|
# CHECK: ldnp d2, d3, [x30, #-8]
|
|
0x23 0x95 0x1f 0x6c
|
|
0x47 0x2d 0x20 0x6c
|
|
0xc2 0x8f 0x7f 0x6c
|
|
|
|
# CHECK: stnp q3, q5, [sp]
|
|
# CHECK: stnp q17, q19, [sp, #1008]
|
|
# CHECK: ldnp q23, q29, [x1, #-1024]
|
|
0xe3 0x17 0x0 0xac
|
|
0xf1 0xcf 0x1f 0xac
|
|
0x37 0x74 0x60 0xac
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Logical (immediate)
|
|
#------------------------------------------------------------------------------
|
|
# CHECK: orr w3, w9, #0xffff0000
|
|
# CHECK: orr wsp, w10, #0xe00000ff
|
|
# CHECK: orr w9, w10, #0x3ff
|
|
0x23 0x3d 0x10 0x32
|
|
0x5f 0x29 0x3 0x32
|
|
0x49 0x25 0x0 0x32
|
|
|
|
# CHECK: and w14, w15, #0x80008000
|
|
# CHECK: and w12, w13, #0xffc3ffc3
|
|
# CHECK: and w11, wzr, #0x30003
|
|
0xee 0x81 0x1 0x12
|
|
0xac 0xad 0xa 0x12
|
|
0xeb 0x87 0x0 0x12
|
|
|
|
# CHECK: eor w3, w6, #0xe0e0e0e0
|
|
# CHECK: eor wsp, wzr, #0x3030303
|
|
# CHECK: eor w16, w17, #0x81818181
|
|
0xc3 0xc8 0x3 0x52
|
|
0xff 0xc7 0x0 0x52
|
|
0x30 0xc6 0x1 0x52
|
|
|
|
# CHECK: {{ands wzr,|tst}} w18, #0xcccccccc
|
|
# CHECK: ands w19, w20, #0x33333333
|
|
# CHECK: ands w21, w22, #0x99999999
|
|
0x5f 0xe6 0x2 0x72
|
|
0x93 0xe6 0x0 0x72
|
|
0xd5 0xe6 0x1 0x72
|
|
|
|
# CHECK: {{ands wzr,|tst}} w3, #0xaaaaaaaa
|
|
# CHECK: {{ands wzr,|tst}} wzr, #0x55555555
|
|
0x7f 0xf0 0x1 0x72
|
|
0xff 0xf3 0x0 0x72
|
|
|
|
# CHECK: eor x3, x5, #0xffffffffc000000
|
|
# CHECK: and x9, x10, #0x7fffffffffff
|
|
# CHECK: orr x11, x12, #0x8000000000000fff
|
|
0xa3 0x84 0x66 0xd2
|
|
0x49 0xb9 0x40 0x92
|
|
0x8b 0x31 0x41 0xb2
|
|
|
|
# CHECK: orr x3, x9, #0xffff0000ffff0000
|
|
# CHECK: orr sp, x10, #0xe00000ffe00000ff
|
|
# CHECK: orr x9, x10, #0x3ff000003ff
|
|
0x23 0x3d 0x10 0xb2
|
|
0x5f 0x29 0x3 0xb2
|
|
0x49 0x25 0x0 0xb2
|
|
|
|
# CHECK: and x14, x15, #0x8000800080008000
|
|
# CHECK: and x12, x13, #0xffc3ffc3ffc3ffc3
|
|
# CHECK: and x11, xzr, #0x3000300030003
|
|
0xee 0x81 0x1 0x92
|
|
0xac 0xad 0xa 0x92
|
|
0xeb 0x87 0x0 0x92
|
|
|
|
# CHECK: eor x3, x6, #0xe0e0e0e0e0e0e0e0
|
|
# CHECK: eor sp, xzr, #0x303030303030303
|
|
# CHECK: eor x16, x17, #0x8181818181818181
|
|
0xc3 0xc8 0x3 0xd2
|
|
0xff 0xc7 0x0 0xd2
|
|
0x30 0xc6 0x1 0xd2
|
|
|
|
# CHECK: {{ands xzr,|tst}} x18, #0xcccccccccccccccc
|
|
# CHECK: ands x19, x20, #0x3333333333333333
|
|
# CHECK: ands x21, x22, #0x9999999999999999
|
|
0x5f 0xe6 0x2 0xf2
|
|
0x93 0xe6 0x0 0xf2
|
|
0xd5 0xe6 0x1 0xf2
|
|
|
|
# CHECK: {{ands xzr,|tst}} x3, #0xaaaaaaaaaaaaaaaa
|
|
# CHECK: {{ands xzr,|tst}} xzr, #0x5555555555555555
|
|
0x7f 0xf0 0x1 0xf2
|
|
0xff 0xf3 0x0 0xf2
|
|
|
|
# CHECK: orr w3, wzr, #0xf000f
|
|
# CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa
|
|
0xe3 0x8f 0x0 0x32
|
|
0xea 0xf3 0x1 0xb2
|
|
|
|
# CHECK: orr w3, wzr, #0xffff
|
|
# CHECK: orr x9, xzr, #0xffff00000000
|
|
0xe3 0x3f 0x0 0x32
|
|
0xe9 0x3f 0x60 0xb2
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Logical (shifted register)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: and w12, w23, w21
|
|
# CHECK: and w16, w15, w1, lsl #1
|
|
# CHECK: and w9, w4, w10, lsl #31
|
|
# CHECK: and w3, w30, w11
|
|
# CHECK: and x3, x5, x7, lsl #63
|
|
0xec 0x2 0x15 0xa
|
|
0xf0 0x5 0x1 0xa
|
|
0x89 0x7c 0xa 0xa
|
|
0xc3 0x3 0xb 0xa
|
|
0xa3 0xfc 0x7 0x8a
|
|
|
|
# CHECK: and x5, x14, x19, asr #4
|
|
# CHECK: and w3, w17, w19, ror #31
|
|
# CHECK: and w0, w2, wzr, lsr #17
|
|
# CHECK: and w3, w30, w11, asr
|
|
0xc5 0x11 0x93 0x8a
|
|
0x23 0x7e 0xd3 0xa
|
|
0x40 0x44 0x5f 0xa
|
|
0xc3 0x3 0x8b 0xa
|
|
|
|
# CHECK: and xzr, x4, x26
|
|
# CHECK: and w3, wzr, w20, ror
|
|
# CHECK: and x7, x20, xzr, asr #63
|
|
0x9f 0x0 0x1a 0x8a
|
|
0xe3 0x3 0xd4 0xa
|
|
0x87 0xfe 0x9f 0x8a
|
|
|
|
# CHECK: bic x13, x20, x14, lsl #47
|
|
# CHECK: bic w2, w7, w9
|
|
# CHECK: orr w2, w7, w0, asr #31
|
|
# CHECK: orr x8, x9, x10, lsl #12
|
|
# CHECK: orn x3, x5, x7, asr
|
|
# CHECK: orn w2, w5, w29
|
|
0x8d 0xbe 0x2e 0x8a
|
|
0xe2 0x0 0x29 0xa
|
|
0xe2 0x7c 0x80 0x2a
|
|
0x28 0x31 0xa 0xaa
|
|
0xa3 0x0 0xa7 0xaa
|
|
0xa2 0x0 0x3d 0x2a
|
|
|
|
# CHECK: ands w7, wzr, w9, lsl #1
|
|
# CHECK: ands x3, x5, x20, ror #63
|
|
# CHECK: bics w3, w5, w7
|
|
# CHECK: bics x3, xzr, x3, lsl #1
|
|
# CHECK: tst w3, w7, lsl #31
|
|
# CHECK: tst x2, x20, asr
|
|
0xe7 0x7 0x9 0x6a
|
|
0xa3 0xfc 0xd4 0xea
|
|
0xa3 0x0 0x27 0x6a
|
|
0xe3 0x7 0x23 0xea
|
|
0x7f 0x7c 0x7 0x6a
|
|
0x5f 0x0 0x94 0xea
|
|
|
|
# CHECK: mov x3, x6
|
|
# CHECK: mov x3, xzr
|
|
# CHECK: mov wzr, w2
|
|
# CHECK: mov w3, w5
|
|
0xe3 0x3 0x6 0xaa
|
|
0xe3 0x3 0x1f 0xaa
|
|
0xff 0x3 0x2 0x2a
|
|
0xe3 0x3 0x5 0x2a
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Move wide (immediate)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# N.b. (FIXME) canonical aliases aren't produced here because of
|
|
# limitation in InstAlias. Lots of the "mov[nz]" instructions should
|
|
# be "mov".
|
|
|
|
# CHECK: movz w1, #{{65535|0xffff}}
|
|
# CHECK: movz w2, #0, lsl #16
|
|
# CHECK: movn w2, #{{1234|0x4d2}}
|
|
0xe1 0xff 0x9f 0x52
|
|
0x2 0x0 0xa0 0x52
|
|
0x42 0x9a 0x80 0x12
|
|
|
|
# CHECK: movz x2, #{{1234|0x4d2}}, lsl #32
|
|
# CHECK: movk xzr, #{{4321|0x10e1}}, lsl #48
|
|
0x42 0x9a 0xc0 0xd2
|
|
0x3f 0x1c 0xe2 0xf2
|
|
|
|
# CHECK: movz x2, #0
|
|
# CHECK: movk w3, #0
|
|
# CHECK: movz x4, #0, lsl #16
|
|
# CHECK: movk w5, #0, lsl #16
|
|
# CHECK: movz x6, #0, lsl #32
|
|
# CHECK: movk x7, #0, lsl #32
|
|
# CHECK: movz x8, #0, lsl #48
|
|
# CHECK: movk x9, #0, lsl #48
|
|
0x2 0x0 0x80 0xd2
|
|
0x3 0x0 0x80 0x72
|
|
0x4 0x0 0xa0 0xd2
|
|
0x5 0x0 0xa0 0x72
|
|
0x6 0x0 0xc0 0xd2
|
|
0x7 0x0 0xc0 0xf2
|
|
0x8 0x0 0xe0 0xd2
|
|
0x9 0x0 0xe0 0xf2
|
|
|
|
#------------------------------------------------------------------------------
|
|
# PC-relative addressing
|
|
#------------------------------------------------------------------------------
|
|
|
|
# It's slightly dodgy using immediates here, but harmless enough when
|
|
# it's all that's available.
|
|
|
|
# CHECK: adr x2, #1600
|
|
# CHECK: adrp x21, #6553600
|
|
# CHECK: adr x0, #262144
|
|
0x02 0x32 0x00 0x10
|
|
0x15 0x32 0x00 0x90
|
|
0x00 0x00 0x20 0x10
|
|
|
|
#------------------------------------------------------------------------------
|
|
# System
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: nop
|
|
# CHECK: hint #{{127|0x7f}}
|
|
# CHECK: nop
|
|
# CHECK: yield
|
|
# CHECK: wfe
|
|
# CHECK: wfi
|
|
# CHECK: sev
|
|
# CHECK: sevl
|
|
0x1f 0x20 0x3 0xd5
|
|
0xff 0x2f 0x3 0xd5
|
|
0x1f 0x20 0x3 0xd5
|
|
0x3f 0x20 0x3 0xd5
|
|
0x5f 0x20 0x3 0xd5
|
|
0x7f 0x20 0x3 0xd5
|
|
0x9f 0x20 0x3 0xd5
|
|
0xbf 0x20 0x3 0xd5
|
|
|
|
# CHECK: clrex
|
|
# CHECK: clrex #0
|
|
# CHECK: clrex #7
|
|
# CHECK: clrex
|
|
0x5f 0x3f 0x3 0xd5
|
|
0x5f 0x30 0x3 0xd5
|
|
0x5f 0x37 0x3 0xd5
|
|
0x5f 0x3f 0x3 0xd5
|
|
|
|
# CHECK: dsb #0
|
|
# CHECK: dsb #12
|
|
# CHECK: dsb sy
|
|
# CHECK: dsb oshld
|
|
# CHECK: dsb oshst
|
|
# CHECK: dsb osh
|
|
# CHECK: dsb nshld
|
|
# CHECK: dsb nshst
|
|
# CHECK: dsb nsh
|
|
# CHECK: dsb ishld
|
|
# CHECK: dsb ishst
|
|
# CHECK: dsb ish
|
|
# CHECK: dsb ld
|
|
# CHECK: dsb st
|
|
# CHECK: dsb sy
|
|
0x9f 0x30 0x3 0xd5
|
|
0x9f 0x3c 0x3 0xd5
|
|
0x9f 0x3f 0x3 0xd5
|
|
0x9f 0x31 0x3 0xd5
|
|
0x9f 0x32 0x3 0xd5
|
|
0x9f 0x33 0x3 0xd5
|
|
0x9f 0x35 0x3 0xd5
|
|
0x9f 0x36 0x3 0xd5
|
|
0x9f 0x37 0x3 0xd5
|
|
0x9f 0x39 0x3 0xd5
|
|
0x9f 0x3a 0x3 0xd5
|
|
0x9f 0x3b 0x3 0xd5
|
|
0x9f 0x3d 0x3 0xd5
|
|
0x9f 0x3e 0x3 0xd5
|
|
0x9f 0x3f 0x3 0xd5
|
|
|
|
# CHECK: dmb #0
|
|
# CHECK: dmb #12
|
|
# CHECK: dmb sy
|
|
# CHECK: dmb oshld
|
|
# CHECK: dmb oshst
|
|
# CHECK: dmb osh
|
|
# CHECK: dmb nshld
|
|
# CHECK: dmb nshst
|
|
# CHECK: dmb nsh
|
|
# CHECK: dmb ishld
|
|
# CHECK: dmb ishst
|
|
# CHECK: dmb ish
|
|
# CHECK: dmb ld
|
|
# CHECK: dmb st
|
|
# CHECK: dmb sy
|
|
0xbf 0x30 0x3 0xd5
|
|
0xbf 0x3c 0x3 0xd5
|
|
0xbf 0x3f 0x3 0xd5
|
|
0xbf 0x31 0x3 0xd5
|
|
0xbf 0x32 0x3 0xd5
|
|
0xbf 0x33 0x3 0xd5
|
|
0xbf 0x35 0x3 0xd5
|
|
0xbf 0x36 0x3 0xd5
|
|
0xbf 0x37 0x3 0xd5
|
|
0xbf 0x39 0x3 0xd5
|
|
0xbf 0x3a 0x3 0xd5
|
|
0xbf 0x3b 0x3 0xd5
|
|
0xbf 0x3d 0x3 0xd5
|
|
0xbf 0x3e 0x3 0xd5
|
|
0xbf 0x3f 0x3 0xd5
|
|
|
|
# CHECK: isb
|
|
# CHECK: isb #12
|
|
0xdf 0x3f 0x3 0xd5
|
|
0xdf 0x3c 0x3 0xd5
|
|
|
|
# CHECK: msr {{spsel|SPSEL}}, #0
|
|
# CHECK: msr {{daifset|DAIFSET}}, #15
|
|
# CHECK: msr {{daifclr|DAIFCLR}}, #12
|
|
0xbf 0x40 0x0 0xd5
|
|
0xdf 0x4f 0x3 0xd5
|
|
0xff 0x4c 0x3 0xd5
|
|
|
|
# CHECK: sys #7, c5, c9, #7, x5
|
|
# CHECK: sys #0, c15, c15, #2
|
|
# CHECK: sysl x9, #7, c5, c9, #7
|
|
# CHECK: sysl x1, #0, c15, c15, #2
|
|
0xe5 0x59 0xf 0xd5
|
|
0x5f 0xff 0x8 0xd5
|
|
0xe9 0x59 0x2f 0xd5
|
|
0x41 0xff 0x28 0xd5
|
|
|
|
# CHECK: {{sys #0, c7, c1, #0, xzr|ic ialluis}}
|
|
# CHECK: {{sys #0, c7, c5, #0, xzr|ic iallu}}
|
|
# CHECK: {{sys #3, c7, c5, #1|ic ivau}}, x9
|
|
0x1f 0x71 0x8 0xd5
|
|
0x1f 0x75 0x8 0xd5
|
|
0x29 0x75 0xb 0xd5
|
|
|
|
# CHECK: {{sys #3, c7, c4, #1|dc zva}}, x12
|
|
# CHECK: {{sys #0, c7, c6, #1|dc ivac}}, xzr
|
|
# CHECK: {{sys #0, c7, c6, #2|dc isw}}, x2
|
|
# CHECK: {{sys #3, c7, c10, #1|dc cvac}}, x9
|
|
# CHECK: {{sys #0, c7, c10, #2|dc csw}}, x10
|
|
# CHECK: {{sys #3, c7, c11, #1|dc cvau}}, x0
|
|
# CHECK: {{sys #3, c7, c14, #1|dc civac}}, x3
|
|
# CHECK: {{sys #0, c7, c14, #2|dc cisw}}, x30
|
|
0x2c 0x74 0xb 0xd5
|
|
0x3f 0x76 0x8 0xd5
|
|
0x42 0x76 0x8 0xd5
|
|
0x29 0x7a 0xb 0xd5
|
|
0x4a 0x7a 0x8 0xd5
|
|
0x20 0x7b 0xb 0xd5
|
|
0x23 0x7e 0xb 0xd5
|
|
0x5e 0x7e 0x8 0xd5
|
|
|
|
|
|
# CHECK: msr {{teecr32_el1|TEECR32_EL1}}, x12
|
|
# CHECK: msr {{osdtrrx_el1|OSDTRRX_EL1}}, x12
|
|
# CHECK: msr {{mdccint_el1|MDCCINT_EL1}}, x12
|
|
# CHECK: msr {{mdscr_el1|MDSCR_EL1}}, x12
|
|
# CHECK: msr {{osdtrtx_el1|OSDTRTX_EL1}}, x12
|
|
# CHECK: msr {{dbgdtr_el0|DBGDTR_EL0}}, x12
|
|
# CHECK: msr {{dbgdtrtx_el0|DBGDTRTX_EL0}}, x12
|
|
# CHECK: msr {{oseccr_el1|OSECCR_EL1}}, x12
|
|
# CHECK: msr {{dbgvcr32_el2|DBGVCR32_EL2}}, x12
|
|
# CHECK: msr {{dbgbvr0_el1|DBGBVR0_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr1_el1|DBGBVR1_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr2_el1|DBGBVR2_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr3_el1|DBGBVR3_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr4_el1|DBGBVR4_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr5_el1|DBGBVR5_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr6_el1|DBGBVR6_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr7_el1|DBGBVR7_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr8_el1|DBGBVR8_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr9_el1|DBGBVR9_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr10_el1|DBGBVR10_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr11_el1|DBGBVR11_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr12_el1|DBGBVR12_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr13_el1|DBGBVR13_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr14_el1|DBGBVR14_EL1}}, x12
|
|
# CHECK: msr {{dbgbvr15_el1|DBGBVR15_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr0_el1|DBGBCR0_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr1_el1|DBGBCR1_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr2_el1|DBGBCR2_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr3_el1|DBGBCR3_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr4_el1|DBGBCR4_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr5_el1|DBGBCR5_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr6_el1|DBGBCR6_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr7_el1|DBGBCR7_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr8_el1|DBGBCR8_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr9_el1|DBGBCR9_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr10_el1|DBGBCR10_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr11_el1|DBGBCR11_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr12_el1|DBGBCR12_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr13_el1|DBGBCR13_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr14_el1|DBGBCR14_EL1}}, x12
|
|
# CHECK: msr {{dbgbcr15_el1|DBGBCR15_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr0_el1|DBGWVR0_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr1_el1|DBGWVR1_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr2_el1|DBGWVR2_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr3_el1|DBGWVR3_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr4_el1|DBGWVR4_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr5_el1|DBGWVR5_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr6_el1|DBGWVR6_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr7_el1|DBGWVR7_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr8_el1|DBGWVR8_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr9_el1|DBGWVR9_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr10_el1|DBGWVR10_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr11_el1|DBGWVR11_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr12_el1|DBGWVR12_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr13_el1|DBGWVR13_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr14_el1|DBGWVR14_EL1}}, x12
|
|
# CHECK: msr {{dbgwvr15_el1|DBGWVR15_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr0_el1|DBGWCR0_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr1_el1|DBGWCR1_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr2_el1|DBGWCR2_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr3_el1|DBGWCR3_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr4_el1|DBGWCR4_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr5_el1|DBGWCR5_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr6_el1|DBGWCR6_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr7_el1|DBGWCR7_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr8_el1|DBGWCR8_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr9_el1|DBGWCR9_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr10_el1|DBGWCR10_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr11_el1|DBGWCR11_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr12_el1|DBGWCR12_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr13_el1|DBGWCR13_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr14_el1|DBGWCR14_EL1}}, x12
|
|
# CHECK: msr {{dbgwcr15_el1|DBGWCR15_EL1}}, x12
|
|
# CHECK: msr {{teehbr32_el1|TEEHBR32_EL1}}, x12
|
|
# CHECK: msr {{oslar_el1|OSLAR_EL1}}, x12
|
|
# CHECK: msr {{osdlr_el1|OSDLR_EL1}}, x12
|
|
# CHECK: msr {{dbgprcr_el1|DBGPRCR_EL1}}, x12
|
|
# CHECK: msr {{dbgclaimset_el1|DBGCLAIMSET_EL1}}, x12
|
|
# CHECK: msr {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}, x12
|
|
# CHECK: msr {{csselr_el1|CSSELR_EL1}}, x12
|
|
# CHECK: msr {{vpidr_el2|VPIDR_EL2}}, x12
|
|
# CHECK: msr {{vmpidr_el2|VMPIDR_EL2}}, x12
|
|
# CHECK: msr {{sctlr_el1|SCTLR_EL1}}, x12
|
|
# CHECK: msr {{sctlr_el2|SCTLR_EL2}}, x12
|
|
# CHECK: msr {{sctlr_el3|SCTLR_EL3}}, x12
|
|
# CHECK: msr {{actlr_el1|ACTLR_EL1}}, x12
|
|
# CHECK: msr {{actlr_el2|ACTLR_EL2}}, x12
|
|
# CHECK: msr {{actlr_el3|ACTLR_EL3}}, x12
|
|
# CHECK: msr {{cpacr_el1|CPACR_EL1}}, x12
|
|
# CHECK: msr {{hcr_el2|HCR_EL2}}, x12
|
|
# CHECK: msr {{scr_el3|SCR_EL3}}, x12
|
|
# CHECK: msr {{mdcr_el2|MDCR_EL2}}, x12
|
|
# CHECK: msr {{sder32_el3|SDER32_EL3}}, x12
|
|
# CHECK: msr {{cptr_el2|CPTR_EL2}}, x12
|
|
# CHECK: msr {{cptr_el3|CPTR_EL3}}, x12
|
|
# CHECK: msr {{hstr_el2|HSTR_EL2}}, x12
|
|
# CHECK: msr {{hacr_el2|HACR_EL2}}, x12
|
|
# CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12
|
|
# CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12
|
|
# CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12
|
|
# CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12
|
|
# CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12
|
|
# CHECK: msr {{tcr_el1|TCR_EL1}}, x12
|
|
# CHECK: msr {{tcr_el2|TCR_EL2}}, x12
|
|
# CHECK: msr {{tcr_el3|TCR_EL3}}, x12
|
|
# CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12
|
|
# CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12
|
|
# CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12
|
|
# CHECK: msr {{spsr_el1|SPSR_EL1}}, x12
|
|
# CHECK: msr {{spsr_el2|SPSR_EL2}}, x12
|
|
# CHECK: msr {{spsr_el3|SPSR_EL3}}, x12
|
|
# CHECK: msr {{elr_el1|ELR_EL1}}, x12
|
|
# CHECK: msr {{elr_el2|ELR_EL2}}, x12
|
|
# CHECK: msr {{elr_el3|ELR_EL3}}, x12
|
|
# CHECK: msr {{sp_el0|SP_EL0}}, x12
|
|
# CHECK: msr {{sp_el1|SP_EL1}}, x12
|
|
# CHECK: msr {{sp_el2|SP_EL2}}, x12
|
|
# CHECK: msr {{spsel|SPSEL}}, x12
|
|
# CHECK: msr {{nzcv|NZCV}}, x12
|
|
# CHECK: msr {{daif|DAIF}}, x12
|
|
# CHECK: msr {{currentel|CURRENTEL}}, x12
|
|
# CHECK: msr {{spsr_irq|SPSR_IRQ}}, x12
|
|
# CHECK: msr {{spsr_abt|SPSR_ABT}}, x12
|
|
# CHECK: msr {{spsr_und|SPSR_UND}}, x12
|
|
# CHECK: msr {{spsr_fiq|SPSR_FIQ}}, x12
|
|
# CHECK: msr {{fpcr|FPCR}}, x12
|
|
# CHECK: msr {{fpsr|FPSR}}, x12
|
|
# CHECK: msr {{dspsr_el0|DSPSR_EL0}}, x12
|
|
# CHECK: msr {{dlr_el0|DLR_EL0}}, x12
|
|
# CHECK: msr {{ifsr32_el2|IFSR32_EL2}}, x12
|
|
# CHECK: msr {{afsr0_el1|AFSR0_EL1}}, x12
|
|
# CHECK: msr {{afsr0_el2|AFSR0_EL2}}, x12
|
|
# CHECK: msr {{afsr0_el3|AFSR0_EL3}}, x12
|
|
# CHECK: msr {{afsr1_el1|AFSR1_EL1}}, x12
|
|
# CHECK: msr {{afsr1_el2|AFSR1_EL2}}, x12
|
|
# CHECK: msr {{afsr1_el3|AFSR1_EL3}}, x12
|
|
# CHECK: msr {{esr_el1|ESR_EL1}}, x12
|
|
# CHECK: msr {{esr_el2|ESR_EL2}}, x12
|
|
# CHECK: msr {{esr_el3|ESR_EL3}}, x12
|
|
# CHECK: msr {{fpexc32_el2|FPEXC32_EL2}}, x12
|
|
# CHECK: msr {{far_el1|FAR_EL1}}, x12
|
|
# CHECK: msr {{far_el2|FAR_EL2}}, x12
|
|
# CHECK: msr {{far_el3|FAR_EL3}}, x12
|
|
# CHECK: msr {{hpfar_el2|HPFAR_EL2}}, x12
|
|
# CHECK: msr {{par_el1|PAR_EL1}}, x12
|
|
# CHECK: msr {{pmcr_el0|PMCR_EL0}}, x12
|
|
# CHECK: msr {{pmcntenset_el0|PMCNTENSET_EL0}}, x12
|
|
# CHECK: msr {{pmcntenclr_el0|PMCNTENCLR_EL0}}, x12
|
|
# CHECK: msr {{pmovsclr_el0|PMOVSCLR_EL0}}, x12
|
|
# CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12
|
|
# CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12
|
|
# CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12
|
|
# CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12
|
|
# CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12
|
|
# CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12
|
|
# CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12
|
|
# CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12
|
|
# CHECK: msr {{mair_el1|MAIR_EL1}}, x12
|
|
# CHECK: msr {{mair_el2|MAIR_EL2}}, x12
|
|
# CHECK: msr {{mair_el3|MAIR_EL3}}, x12
|
|
# CHECK: msr {{amair_el1|AMAIR_EL1}}, x12
|
|
# CHECK: msr {{amair_el2|AMAIR_EL2}}, x12
|
|
# CHECK: msr {{amair_el3|AMAIR_EL3}}, x12
|
|
# CHECK: msr {{vbar_el1|VBAR_EL1}}, x12
|
|
# CHECK: msr {{vbar_el2|VBAR_EL2}}, x12
|
|
# CHECK: msr {{vbar_el3|VBAR_EL3}}, x12
|
|
# CHECK: msr {{rmr_el1|RMR_EL1}}, x12
|
|
# CHECK: msr {{rmr_el2|RMR_EL2}}, x12
|
|
# CHECK: msr {{rmr_el3|RMR_EL3}}, x12
|
|
# CHECK: msr {{tpidr_el0|TPIDR_EL0}}, x12
|
|
# CHECK: msr {{tpidr_el2|TPIDR_EL2}}, x12
|
|
# CHECK: msr {{tpidr_el3|TPIDR_EL3}}, x12
|
|
# CHECK: msr {{tpidrro_el0|TPIDRRO_EL0}}, x12
|
|
# CHECK: msr {{tpidr_el1|TPIDR_EL1}}, x12
|
|
# CHECK: msr {{cntfrq_el0|CNTFRQ_EL0}}, x12
|
|
# CHECK: msr {{cntvoff_el2|CNTVOFF_EL2}}, x12
|
|
# CHECK: msr {{cntkctl_el1|CNTKCTL_EL1}}, x12
|
|
# CHECK: msr {{cnthctl_el2|CNTHCTL_EL2}}, x12
|
|
# CHECK: msr {{cntp_tval_el0|CNTP_TVAL_EL0}}, x12
|
|
# CHECK: msr {{cnthp_tval_el2|CNTHP_TVAL_EL2}}, x12
|
|
# CHECK: msr {{cntps_tval_el1|CNTPS_TVAL_EL1}}, x12
|
|
# CHECK: msr {{cntp_ctl_el0|CNTP_CTL_EL0}}, x12
|
|
# CHECK: msr {{cnthp_ctl_el2|CNTHP_CTL_EL2}}, x12
|
|
# CHECK: msr {{cntps_ctl_el1|CNTPS_CTL_EL1}}, x12
|
|
# CHECK: msr {{cntp_cval_el0|CNTP_CVAL_EL0}}, x12
|
|
# CHECK: msr {{cnthp_cval_el2|CNTHP_CVAL_EL2}}, x12
|
|
# CHECK: msr {{cntps_cval_el1|CNTPS_CVAL_EL1}}, x12
|
|
# CHECK: msr {{cntv_tval_el0|CNTV_TVAL_EL0}}, x12
|
|
# CHECK: msr {{cntv_ctl_el0|CNTV_CTL_EL0}}, x12
|
|
# CHECK: msr {{cntv_cval_el0|CNTV_CVAL_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr0_el0|PMEVCNTR0_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr1_el0|PMEVCNTR1_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr2_el0|PMEVCNTR2_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr3_el0|PMEVCNTR3_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr4_el0|PMEVCNTR4_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr5_el0|PMEVCNTR5_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr6_el0|PMEVCNTR6_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr7_el0|PMEVCNTR7_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr8_el0|PMEVCNTR8_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr9_el0|PMEVCNTR9_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr10_el0|PMEVCNTR10_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr11_el0|PMEVCNTR11_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr12_el0|PMEVCNTR12_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr13_el0|PMEVCNTR13_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr14_el0|PMEVCNTR14_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr15_el0|PMEVCNTR15_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr16_el0|PMEVCNTR16_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr17_el0|PMEVCNTR17_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr18_el0|PMEVCNTR18_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr19_el0|PMEVCNTR19_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr20_el0|PMEVCNTR20_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr21_el0|PMEVCNTR21_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr22_el0|PMEVCNTR22_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr23_el0|PMEVCNTR23_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr24_el0|PMEVCNTR24_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr25_el0|PMEVCNTR25_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr26_el0|PMEVCNTR26_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr27_el0|PMEVCNTR27_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr28_el0|PMEVCNTR28_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr29_el0|PMEVCNTR29_EL0}}, x12
|
|
# CHECK: msr {{pmevcntr30_el0|PMEVCNTR30_EL0}}, x12
|
|
# CHECK: msr {{pmccfiltr_el0|PMCCFILTR_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper0_el0|PMEVTYPER0_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper1_el0|PMEVTYPER1_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper2_el0|PMEVTYPER2_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper3_el0|PMEVTYPER3_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper4_el0|PMEVTYPER4_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper5_el0|PMEVTYPER5_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper6_el0|PMEVTYPER6_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper7_el0|PMEVTYPER7_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper8_el0|PMEVTYPER8_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper9_el0|PMEVTYPER9_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper10_el0|PMEVTYPER10_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper11_el0|PMEVTYPER11_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper12_el0|PMEVTYPER12_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper13_el0|PMEVTYPER13_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper14_el0|PMEVTYPER14_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper15_el0|PMEVTYPER15_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper16_el0|PMEVTYPER16_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper17_el0|PMEVTYPER17_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper18_el0|PMEVTYPER18_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper19_el0|PMEVTYPER19_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper20_el0|PMEVTYPER20_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper21_el0|PMEVTYPER21_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper22_el0|PMEVTYPER22_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper23_el0|PMEVTYPER23_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper24_el0|PMEVTYPER24_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper25_el0|PMEVTYPER25_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper26_el0|PMEVTYPER26_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper27_el0|PMEVTYPER27_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper28_el0|PMEVTYPER28_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper29_el0|PMEVTYPER29_EL0}}, x12
|
|
# CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12
|
|
# CHECK: mrs x9, {{teecr32_el1|TEECR32_EL1}}
|
|
# CHECK: mrs x9, {{osdtrrx_el1|OSDTRRX_EL1}}
|
|
# CHECK: mrs x9, {{mdccsr_el0|MDCCSR_EL0}}
|
|
# CHECK: mrs x9, {{mdccint_el1|MDCCINT_EL1}}
|
|
# CHECK: mrs x9, {{mdscr_el1|MDSCR_EL1}}
|
|
# CHECK: mrs x9, {{osdtrtx_el1|OSDTRTX_EL1}}
|
|
# CHECK: mrs x9, {{dbgdtr_el0|DBGDTR_EL0}}
|
|
# CHECK: mrs x9, {{dbgdtrrx_el0|DBGDTRRX_EL0}}
|
|
# CHECK: mrs x9, {{oseccr_el1|OSECCR_EL1}}
|
|
# CHECK: mrs x9, {{dbgvcr32_el2|DBGVCR32_EL2}}
|
|
# CHECK: mrs x9, {{dbgbvr0_el1|DBGBVR0_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr1_el1|DBGBVR1_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr2_el1|DBGBVR2_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr3_el1|DBGBVR3_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr4_el1|DBGBVR4_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr5_el1|DBGBVR5_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr6_el1|DBGBVR6_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr7_el1|DBGBVR7_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr8_el1|DBGBVR8_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr9_el1|DBGBVR9_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr10_el1|DBGBVR10_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr11_el1|DBGBVR11_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr12_el1|DBGBVR12_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr13_el1|DBGBVR13_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr14_el1|DBGBVR14_EL1}}
|
|
# CHECK: mrs x9, {{dbgbvr15_el1|DBGBVR15_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr0_el1|DBGBCR0_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr1_el1|DBGBCR1_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr2_el1|DBGBCR2_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr3_el1|DBGBCR3_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr4_el1|DBGBCR4_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr5_el1|DBGBCR5_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr6_el1|DBGBCR6_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr7_el1|DBGBCR7_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr8_el1|DBGBCR8_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr9_el1|DBGBCR9_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr10_el1|DBGBCR10_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr11_el1|DBGBCR11_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr12_el1|DBGBCR12_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr13_el1|DBGBCR13_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr14_el1|DBGBCR14_EL1}}
|
|
# CHECK: mrs x9, {{dbgbcr15_el1|DBGBCR15_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr0_el1|DBGWVR0_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr1_el1|DBGWVR1_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr2_el1|DBGWVR2_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr3_el1|DBGWVR3_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr4_el1|DBGWVR4_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr5_el1|DBGWVR5_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr6_el1|DBGWVR6_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr7_el1|DBGWVR7_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr8_el1|DBGWVR8_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr9_el1|DBGWVR9_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr10_el1|DBGWVR10_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr11_el1|DBGWVR11_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr12_el1|DBGWVR12_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr13_el1|DBGWVR13_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr14_el1|DBGWVR14_EL1}}
|
|
# CHECK: mrs x9, {{dbgwvr15_el1|DBGWVR15_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr0_el1|DBGWCR0_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr1_el1|DBGWCR1_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr2_el1|DBGWCR2_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr3_el1|DBGWCR3_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr4_el1|DBGWCR4_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr5_el1|DBGWCR5_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr6_el1|DBGWCR6_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr7_el1|DBGWCR7_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr8_el1|DBGWCR8_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr9_el1|DBGWCR9_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr10_el1|DBGWCR10_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr11_el1|DBGWCR11_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr12_el1|DBGWCR12_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr13_el1|DBGWCR13_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr14_el1|DBGWCR14_EL1}}
|
|
# CHECK: mrs x9, {{dbgwcr15_el1|DBGWCR15_EL1}}
|
|
# CHECK: mrs x9, {{mdrar_el1|MDRAR_EL1}}
|
|
# CHECK: mrs x9, {{teehbr32_el1|TEEHBR32_EL1}}
|
|
# CHECK: mrs x9, {{oslsr_el1|OSLSR_EL1}}
|
|
# CHECK: mrs x9, {{osdlr_el1|OSDLR_EL1}}
|
|
# CHECK: mrs x9, {{dbgprcr_el1|DBGPRCR_EL1}}
|
|
# CHECK: mrs x9, {{dbgclaimset_el1|DBGCLAIMSET_EL1}}
|
|
# CHECK: mrs x9, {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}
|
|
# CHECK: mrs x9, {{dbgauthstatus_el1|DBGAUTHSTATUS_EL1}}
|
|
# CHECK: mrs x9, {{midr_el1|MIDR_EL1}}
|
|
# CHECK: mrs x9, {{ccsidr_el1|CCSIDR_EL1}}
|
|
# CHECK: mrs x9, {{csselr_el1|CSSELR_EL1}}
|
|
# CHECK: mrs x9, {{vpidr_el2|VPIDR_EL2}}
|
|
# CHECK: mrs x9, {{clidr_el1|CLIDR_EL1}}
|
|
# CHECK: mrs x9, {{ctr_el0|CTR_EL0}}
|
|
# CHECK: mrs x9, {{mpidr_el1|MPIDR_EL1}}
|
|
# CHECK: mrs x9, {{vmpidr_el2|VMPIDR_EL2}}
|
|
# CHECK: mrs x9, {{revidr_el1|REVIDR_EL1}}
|
|
# CHECK: mrs x9, {{aidr_el1|AIDR_EL1}}
|
|
# CHECK: mrs x9, {{dczid_el0|DCZID_EL0}}
|
|
# CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}}
|
|
# CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}}
|
|
# CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}}
|
|
# CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}}
|
|
# CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}}
|
|
# CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}}
|
|
# CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}}
|
|
# CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}}
|
|
# CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}}
|
|
# CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}}
|
|
# CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}}
|
|
# CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}}
|
|
# CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}}
|
|
# CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}}
|
|
# CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}}
|
|
# CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}}
|
|
# CHECK: mrs x9, {{mvfr2_el1|MVFR2_EL1}}
|
|
# CHECK: mrs x9, {{id_aa64pfr0_el1|ID_AA64PFR0_EL1}}
|
|
# CHECK: mrs x9, {{id_aa64pfr1_el1|ID_AA64PFR1_EL1}}
|
|
# CHECK: mrs x9, {{id_aa64dfr0_el1|ID_AA64DFR0_EL1}}
|
|
# CHECK: mrs x9, {{id_aa64dfr1_el1|ID_AA64DFR1_EL1}}
|
|
# CHECK: mrs x9, {{id_aa64afr0_el1|ID_AA64AFR0_EL1}}
|
|
# CHECK: mrs x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}}
|
|
# CHECK: mrs x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}}
|
|
# CHECK: mrs x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}}
|
|
# CHECK: mrs x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}}
|
|
# CHECK: mrs x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}}
|
|
# CHECK: mrs x9, {{sctlr_el1|SCTLR_EL1}}
|
|
# CHECK: mrs x9, {{sctlr_el2|SCTLR_EL2}}
|
|
# CHECK: mrs x9, {{sctlr_el3|SCTLR_EL3}}
|
|
# CHECK: mrs x9, {{actlr_el1|ACTLR_EL1}}
|
|
# CHECK: mrs x9, {{actlr_el2|ACTLR_EL2}}
|
|
# CHECK: mrs x9, {{actlr_el3|ACTLR_EL3}}
|
|
# CHECK: mrs x9, {{cpacr_el1|CPACR_EL1}}
|
|
# CHECK: mrs x9, {{hcr_el2|HCR_EL2}}
|
|
# CHECK: mrs x9, {{scr_el3|SCR_EL3}}
|
|
# CHECK: mrs x9, {{mdcr_el2|MDCR_EL2}}
|
|
# CHECK: mrs x9, {{sder32_el3|SDER32_EL3}}
|
|
# CHECK: mrs x9, {{cptr_el2|CPTR_EL2}}
|
|
# CHECK: mrs x9, {{cptr_el3|CPTR_EL3}}
|
|
# CHECK: mrs x9, {{hstr_el2|HSTR_EL2}}
|
|
# CHECK: mrs x9, {{hacr_el2|HACR_EL2}}
|
|
# CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}}
|
|
# CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}}
|
|
# CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}}
|
|
# CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}}
|
|
# CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}}
|
|
# CHECK: mrs x9, {{tcr_el1|TCR_EL1}}
|
|
# CHECK: mrs x9, {{tcr_el2|TCR_EL2}}
|
|
# CHECK: mrs x9, {{tcr_el3|TCR_EL3}}
|
|
# CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}}
|
|
# CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}}
|
|
# CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}}
|
|
# CHECK: mrs x9, {{spsr_el1|SPSR_EL1}}
|
|
# CHECK: mrs x9, {{spsr_el2|SPSR_EL2}}
|
|
# CHECK: mrs x9, {{spsr_el3|SPSR_EL3}}
|
|
# CHECK: mrs x9, {{elr_el1|ELR_EL1}}
|
|
# CHECK: mrs x9, {{elr_el2|ELR_EL2}}
|
|
# CHECK: mrs x9, {{elr_el3|ELR_EL3}}
|
|
# CHECK: mrs x9, {{sp_el0|SP_EL0}}
|
|
# CHECK: mrs x9, {{sp_el1|SP_EL1}}
|
|
# CHECK: mrs x9, {{sp_el2|SP_EL2}}
|
|
# CHECK: mrs x9, {{spsel|SPSEL}}
|
|
# CHECK: mrs x9, {{nzcv|NZCV}}
|
|
# CHECK: mrs x9, {{daif|DAIF}}
|
|
# CHECK: mrs x9, {{currentel|CURRENTEL}}
|
|
# CHECK: mrs x9, {{spsr_irq|SPSR_IRQ}}
|
|
# CHECK: mrs x9, {{spsr_abt|SPSR_ABT}}
|
|
# CHECK: mrs x9, {{spsr_und|SPSR_UND}}
|
|
# CHECK: mrs x9, {{spsr_fiq|SPSR_FIQ}}
|
|
# CHECK: mrs x9, {{fpcr|FPCR}}
|
|
# CHECK: mrs x9, {{fpsr|FPSR}}
|
|
# CHECK: mrs x9, {{dspsr_el0|DSPSR_EL0}}
|
|
# CHECK: mrs x9, {{dlr_el0|DLR_EL0}}
|
|
# CHECK: mrs x9, {{ifsr32_el2|IFSR32_EL2}}
|
|
# CHECK: mrs x9, {{afsr0_el1|AFSR0_EL1}}
|
|
# CHECK: mrs x9, {{afsr0_el2|AFSR0_EL2}}
|
|
# CHECK: mrs x9, {{afsr0_el3|AFSR0_EL3}}
|
|
# CHECK: mrs x9, {{afsr1_el1|AFSR1_EL1}}
|
|
# CHECK: mrs x9, {{afsr1_el2|AFSR1_EL2}}
|
|
# CHECK: mrs x9, {{afsr1_el3|AFSR1_EL3}}
|
|
# CHECK: mrs x9, {{esr_el1|ESR_EL1}}
|
|
# CHECK: mrs x9, {{esr_el2|ESR_EL2}}
|
|
# CHECK: mrs x9, {{esr_el3|ESR_EL3}}
|
|
# CHECK: mrs x9, {{fpexc32_el2|FPEXC32_EL2}}
|
|
# CHECK: mrs x9, {{far_el1|FAR_EL1}}
|
|
# CHECK: mrs x9, {{far_el2|FAR_EL2}}
|
|
# CHECK: mrs x9, {{far_el3|FAR_EL3}}
|
|
# CHECK: mrs x9, {{hpfar_el2|HPFAR_EL2}}
|
|
# CHECK: mrs x9, {{par_el1|PAR_EL1}}
|
|
# CHECK: mrs x9, {{pmcr_el0|PMCR_EL0}}
|
|
# CHECK: mrs x9, {{pmcntenset_el0|PMCNTENSET_EL0}}
|
|
# CHECK: mrs x9, {{pmcntenclr_el0|PMCNTENCLR_EL0}}
|
|
# CHECK: mrs x9, {{pmovsclr_el0|PMOVSCLR_EL0}}
|
|
# CHECK: mrs x9, {{pmselr_el0|PMSELR_EL0}}
|
|
# CHECK: mrs x9, {{pmceid0_el0|PMCEID0_EL0}}
|
|
# CHECK: mrs x9, {{pmceid1_el0|PMCEID1_EL0}}
|
|
# CHECK: mrs x9, {{pmccntr_el0|PMCCNTR_EL0}}
|
|
# CHECK: mrs x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}}
|
|
# CHECK: mrs x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}}
|
|
# CHECK: mrs x9, {{pmuserenr_el0|PMUSERENR_EL0}}
|
|
# CHECK: mrs x9, {{pmintenset_el1|PMINTENSET_EL1}}
|
|
# CHECK: mrs x9, {{pmintenclr_el1|PMINTENCLR_EL1}}
|
|
# CHECK: mrs x9, {{pmovsset_el0|PMOVSSET_EL0}}
|
|
# CHECK: mrs x9, {{mair_el1|MAIR_EL1}}
|
|
# CHECK: mrs x9, {{mair_el2|MAIR_EL2}}
|
|
# CHECK: mrs x9, {{mair_el3|MAIR_EL3}}
|
|
# CHECK: mrs x9, {{amair_el1|AMAIR_EL1}}
|
|
# CHECK: mrs x9, {{amair_el2|AMAIR_EL2}}
|
|
# CHECK: mrs x9, {{amair_el3|AMAIR_EL3}}
|
|
# CHECK: mrs x9, {{vbar_el1|VBAR_EL1}}
|
|
# CHECK: mrs x9, {{vbar_el2|VBAR_EL2}}
|
|
# CHECK: mrs x9, {{vbar_el3|VBAR_EL3}}
|
|
# CHECK: mrs x9, {{rvbar_el1|RVBAR_EL1}}
|
|
# CHECK: mrs x9, {{rvbar_el2|RVBAR_EL2}}
|
|
# CHECK: mrs x9, {{rvbar_el3|RVBAR_EL3}}
|
|
# CHECK: mrs x9, {{rmr_el1|RMR_EL1}}
|
|
# CHECK: mrs x9, {{rmr_el2|RMR_EL2}}
|
|
# CHECK: mrs x9, {{rmr_el3|RMR_EL3}}
|
|
# CHECK: mrs x9, {{isr_el1|ISR_EL1}}
|
|
# CHECK: mrs x9, {{contextidr_el1|CONTEXTIDR_EL1}}
|
|
# CHECK: mrs x9, {{tpidr_el0|TPIDR_EL0}}
|
|
# CHECK: mrs x9, {{tpidr_el2|TPIDR_EL2}}
|
|
# CHECK: mrs x9, {{tpidr_el3|TPIDR_EL3}}
|
|
# CHECK: mrs x9, {{tpidrro_el0|TPIDRRO_EL0}}
|
|
# CHECK: mrs x9, {{tpidr_el1|TPIDR_EL1}}
|
|
# CHECK: mrs x9, {{cntfrq_el0|CNTFRQ_EL0}}
|
|
# CHECK: mrs x9, {{cntpct_el0|CNTPCT_EL0}}
|
|
# CHECK: mrs x9, {{cntvct_el0|CNTVCT_EL0}}
|
|
# CHECK: mrs x9, {{cntvoff_el2|CNTVOFF_EL2}}
|
|
# CHECK: mrs x9, {{cntkctl_el1|CNTKCTL_EL1}}
|
|
# CHECK: mrs x9, {{cnthctl_el2|CNTHCTL_EL2}}
|
|
# CHECK: mrs x9, {{cntp_tval_el0|CNTP_TVAL_EL0}}
|
|
# CHECK: mrs x9, {{cnthp_tval_el2|CNTHP_TVAL_EL2}}
|
|
# CHECK: mrs x9, {{cntps_tval_el1|CNTPS_TVAL_EL1}}
|
|
# CHECK: mrs x9, {{cntp_ctl_el0|CNTP_CTL_EL0}}
|
|
# CHECK: mrs x9, {{cnthp_ctl_el2|CNTHP_CTL_EL2}}
|
|
# CHECK: mrs x9, {{cntps_ctl_el1|CNTPS_CTL_EL1}}
|
|
# CHECK: mrs x9, {{cntp_cval_el0|CNTP_CVAL_EL0}}
|
|
# CHECK: mrs x9, {{cnthp_cval_el2|CNTHP_CVAL_EL2}}
|
|
# CHECK: mrs x9, {{cntps_cval_el1|CNTPS_CVAL_EL1}}
|
|
# CHECK: mrs x9, {{cntv_tval_el0|CNTV_TVAL_EL0}}
|
|
# CHECK: mrs x9, {{cntv_ctl_el0|CNTV_CTL_EL0}}
|
|
# CHECK: mrs x9, {{cntv_cval_el0|CNTV_CVAL_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr0_el0|PMEVCNTR0_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr1_el0|PMEVCNTR1_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr2_el0|PMEVCNTR2_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr3_el0|PMEVCNTR3_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr4_el0|PMEVCNTR4_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr5_el0|PMEVCNTR5_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr6_el0|PMEVCNTR6_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr7_el0|PMEVCNTR7_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr8_el0|PMEVCNTR8_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr9_el0|PMEVCNTR9_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr10_el0|PMEVCNTR10_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr11_el0|PMEVCNTR11_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr12_el0|PMEVCNTR12_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr13_el0|PMEVCNTR13_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr14_el0|PMEVCNTR14_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr15_el0|PMEVCNTR15_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr16_el0|PMEVCNTR16_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr17_el0|PMEVCNTR17_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr18_el0|PMEVCNTR18_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr19_el0|PMEVCNTR19_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr20_el0|PMEVCNTR20_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr21_el0|PMEVCNTR21_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr22_el0|PMEVCNTR22_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr23_el0|PMEVCNTR23_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr24_el0|PMEVCNTR24_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr25_el0|PMEVCNTR25_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr26_el0|PMEVCNTR26_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr27_el0|PMEVCNTR27_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr28_el0|PMEVCNTR28_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr29_el0|PMEVCNTR29_EL0}}
|
|
# CHECK: mrs x9, {{pmevcntr30_el0|PMEVCNTR30_EL0}}
|
|
# CHECK: mrs x9, {{pmccfiltr_el0|PMCCFILTR_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper0_el0|PMEVTYPER0_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper1_el0|PMEVTYPER1_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper2_el0|PMEVTYPER2_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper3_el0|PMEVTYPER3_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper4_el0|PMEVTYPER4_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper5_el0|PMEVTYPER5_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper6_el0|PMEVTYPER6_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper7_el0|PMEVTYPER7_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper8_el0|PMEVTYPER8_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper9_el0|PMEVTYPER9_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper10_el0|PMEVTYPER10_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper11_el0|PMEVTYPER11_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper12_el0|PMEVTYPER12_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper13_el0|PMEVTYPER13_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper14_el0|PMEVTYPER14_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper15_el0|PMEVTYPER15_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper16_el0|PMEVTYPER16_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper17_el0|PMEVTYPER17_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper18_el0|PMEVTYPER18_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper19_el0|PMEVTYPER19_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper20_el0|PMEVTYPER20_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper21_el0|PMEVTYPER21_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper22_el0|PMEVTYPER22_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper23_el0|PMEVTYPER23_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper24_el0|PMEVTYPER24_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper25_el0|PMEVTYPER25_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper26_el0|PMEVTYPER26_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper27_el0|PMEVTYPER27_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper28_el0|PMEVTYPER28_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper29_el0|PMEVTYPER29_EL0}}
|
|
# CHECK: mrs x9, {{pmevtyper30_el0|PMEVTYPER30_EL0}}
|
|
|
|
0xc 0x0 0x12 0xd5
|
|
0x4c 0x0 0x10 0xd5
|
|
0xc 0x2 0x10 0xd5
|
|
0x4c 0x2 0x10 0xd5
|
|
0x4c 0x3 0x10 0xd5
|
|
0xc 0x4 0x13 0xd5
|
|
0xc 0x5 0x13 0xd5
|
|
0x4c 0x6 0x10 0xd5
|
|
0xc 0x7 0x14 0xd5
|
|
0x8c 0x0 0x10 0xd5
|
|
0x8c 0x1 0x10 0xd5
|
|
0x8c 0x2 0x10 0xd5
|
|
0x8c 0x3 0x10 0xd5
|
|
0x8c 0x4 0x10 0xd5
|
|
0x8c 0x5 0x10 0xd5
|
|
0x8c 0x6 0x10 0xd5
|
|
0x8c 0x7 0x10 0xd5
|
|
0x8c 0x8 0x10 0xd5
|
|
0x8c 0x9 0x10 0xd5
|
|
0x8c 0xa 0x10 0xd5
|
|
0x8c 0xb 0x10 0xd5
|
|
0x8c 0xc 0x10 0xd5
|
|
0x8c 0xd 0x10 0xd5
|
|
0x8c 0xe 0x10 0xd5
|
|
0x8c 0xf 0x10 0xd5
|
|
0xac 0x0 0x10 0xd5
|
|
0xac 0x1 0x10 0xd5
|
|
0xac 0x2 0x10 0xd5
|
|
0xac 0x3 0x10 0xd5
|
|
0xac 0x4 0x10 0xd5
|
|
0xac 0x5 0x10 0xd5
|
|
0xac 0x6 0x10 0xd5
|
|
0xac 0x7 0x10 0xd5
|
|
0xac 0x8 0x10 0xd5
|
|
0xac 0x9 0x10 0xd5
|
|
0xac 0xa 0x10 0xd5
|
|
0xac 0xb 0x10 0xd5
|
|
0xac 0xc 0x10 0xd5
|
|
0xac 0xd 0x10 0xd5
|
|
0xac 0xe 0x10 0xd5
|
|
0xac 0xf 0x10 0xd5
|
|
0xcc 0x0 0x10 0xd5
|
|
0xcc 0x1 0x10 0xd5
|
|
0xcc 0x2 0x10 0xd5
|
|
0xcc 0x3 0x10 0xd5
|
|
0xcc 0x4 0x10 0xd5
|
|
0xcc 0x5 0x10 0xd5
|
|
0xcc 0x6 0x10 0xd5
|
|
0xcc 0x7 0x10 0xd5
|
|
0xcc 0x8 0x10 0xd5
|
|
0xcc 0x9 0x10 0xd5
|
|
0xcc 0xa 0x10 0xd5
|
|
0xcc 0xb 0x10 0xd5
|
|
0xcc 0xc 0x10 0xd5
|
|
0xcc 0xd 0x10 0xd5
|
|
0xcc 0xe 0x10 0xd5
|
|
0xcc 0xf 0x10 0xd5
|
|
0xec 0x0 0x10 0xd5
|
|
0xec 0x1 0x10 0xd5
|
|
0xec 0x2 0x10 0xd5
|
|
0xec 0x3 0x10 0xd5
|
|
0xec 0x4 0x10 0xd5
|
|
0xec 0x5 0x10 0xd5
|
|
0xec 0x6 0x10 0xd5
|
|
0xec 0x7 0x10 0xd5
|
|
0xec 0x8 0x10 0xd5
|
|
0xec 0x9 0x10 0xd5
|
|
0xec 0xa 0x10 0xd5
|
|
0xec 0xb 0x10 0xd5
|
|
0xec 0xc 0x10 0xd5
|
|
0xec 0xd 0x10 0xd5
|
|
0xec 0xe 0x10 0xd5
|
|
0xec 0xf 0x10 0xd5
|
|
0xc 0x10 0x12 0xd5
|
|
0x8c 0x10 0x10 0xd5
|
|
0x8c 0x13 0x10 0xd5
|
|
0x8c 0x14 0x10 0xd5
|
|
0xcc 0x78 0x10 0xd5
|
|
0xcc 0x79 0x10 0xd5
|
|
0xc 0x0 0x1a 0xd5
|
|
0xc 0x0 0x1c 0xd5
|
|
0xac 0x0 0x1c 0xd5
|
|
0xc 0x10 0x18 0xd5
|
|
0xc 0x10 0x1c 0xd5
|
|
0xc 0x10 0x1e 0xd5
|
|
0x2c 0x10 0x18 0xd5
|
|
0x2c 0x10 0x1c 0xd5
|
|
0x2c 0x10 0x1e 0xd5
|
|
0x4c 0x10 0x18 0xd5
|
|
0xc 0x11 0x1c 0xd5
|
|
0xc 0x11 0x1e 0xd5
|
|
0x2c 0x11 0x1c 0xd5
|
|
0x2c 0x11 0x1e 0xd5
|
|
0x4c 0x11 0x1c 0xd5
|
|
0x4c 0x11 0x1e 0xd5
|
|
0x6c 0x11 0x1c 0xd5
|
|
0xec 0x11 0x1c 0xd5
|
|
0x2c 0x13 0x1e 0xd5
|
|
0xc 0x20 0x18 0xd5
|
|
0xc 0x20 0x1c 0xd5
|
|
0xc 0x20 0x1e 0xd5
|
|
0x2c 0x20 0x18 0xd5
|
|
0x4c 0x20 0x18 0xd5
|
|
0x4c 0x20 0x1c 0xd5
|
|
0x4c 0x20 0x1e 0xd5
|
|
0xc 0x21 0x1c 0xd5
|
|
0x4c 0x21 0x1c 0xd5
|
|
0xc 0x30 0x1c 0xd5
|
|
0xc 0x40 0x18 0xd5
|
|
0xc 0x40 0x1c 0xd5
|
|
0xc 0x40 0x1e 0xd5
|
|
0x2c 0x40 0x18 0xd5
|
|
0x2c 0x40 0x1c 0xd5
|
|
0x2c 0x40 0x1e 0xd5
|
|
0xc 0x41 0x18 0xd5
|
|
0xc 0x41 0x1c 0xd5
|
|
0xc 0x41 0x1e 0xd5
|
|
0xc 0x42 0x18 0xd5
|
|
0xc 0x42 0x1b 0xd5
|
|
0x2c 0x42 0x1b 0xd5
|
|
0x4c 0x42 0x18 0xd5
|
|
0xc 0x43 0x1c 0xd5
|
|
0x2c 0x43 0x1c 0xd5
|
|
0x4c 0x43 0x1c 0xd5
|
|
0x6c 0x43 0x1c 0xd5
|
|
0xc 0x44 0x1b 0xd5
|
|
0x2c 0x44 0x1b 0xd5
|
|
0xc 0x45 0x1b 0xd5
|
|
0x2c 0x45 0x1b 0xd5
|
|
0x2c 0x50 0x1c 0xd5
|
|
0xc 0x51 0x18 0xd5
|
|
0xc 0x51 0x1c 0xd5
|
|
0xc 0x51 0x1e 0xd5
|
|
0x2c 0x51 0x18 0xd5
|
|
0x2c 0x51 0x1c 0xd5
|
|
0x2c 0x51 0x1e 0xd5
|
|
0xc 0x52 0x18 0xd5
|
|
0xc 0x52 0x1c 0xd5
|
|
0xc 0x52 0x1e 0xd5
|
|
0xc 0x53 0x1c 0xd5
|
|
0xc 0x60 0x18 0xd5
|
|
0xc 0x60 0x1c 0xd5
|
|
0xc 0x60 0x1e 0xd5
|
|
0x8c 0x60 0x1c 0xd5
|
|
0xc 0x74 0x18 0xd5
|
|
0xc 0x9c 0x1b 0xd5
|
|
0x2c 0x9c 0x1b 0xd5
|
|
0x4c 0x9c 0x1b 0xd5
|
|
0x6c 0x9c 0x1b 0xd5
|
|
0xac 0x9c 0x1b 0xd5
|
|
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0xe9 0xee 0x3b 0xd5
|
|
0x9 0xef 0x3b 0xd5
|
|
0x29 0xef 0x3b 0xd5
|
|
0x49 0xef 0x3b 0xd5
|
|
0x69 0xef 0x3b 0xd5
|
|
0x89 0xef 0x3b 0xd5
|
|
0xa9 0xef 0x3b 0xd5
|
|
0xc9 0xef 0x3b 0xd5
|
|
|
|
# CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}}
|
|
# CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}}
|
|
# CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12
|
|
# CHECK: msr {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5
|
|
0xac 0xf1 0x3f 0xd5
|
|
0xed 0xbf 0x3a 0xd5
|
|
0x0c 0xf0 0x18 0xd5
|
|
0xe5 0xbd 0x1f 0xd5
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Test and branch (immediate)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: tbz x12, #62, #0
|
|
# CHECK: tbz x12, #62, #4
|
|
# CHECK: tbz x12, #62, #-32768
|
|
# CHECK: tbnz x12, #60, #32764
|
|
0x0c 0x00 0xf0 0xb6
|
|
0x2c 0x00 0xf0 0xb6
|
|
0x0c 0x00 0xf4 0xb6
|
|
0xec 0xff 0xe3 0xb7
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Unconditional branch (immediate)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: b #4
|
|
# CHECK: b #-4
|
|
# CHECK: b #134217724
|
|
0x01 0x00 0x00 0x14
|
|
0xff 0xff 0xff 0x17
|
|
0xff 0xff 0xff 0x15
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Unconditional branch (register)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: br x20
|
|
# CHECK: blr xzr
|
|
# CHECK: ret x10
|
|
0x80 0x2 0x1f 0xd6
|
|
0xe0 0x3 0x3f 0xd6
|
|
0x40 0x1 0x5f 0xd6
|
|
|
|
# CHECK: ret
|
|
# CHECK: eret
|
|
# CHECK: drps
|
|
0xc0 0x3 0x5f 0xd6
|
|
0xe0 0x3 0x9f 0xd6
|
|
0xe0 0x3 0xbf 0xd6
|
|
|