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The order of registers returned by getCalleeSavedRegs is used to lay out the fixed stack slots for CSRs. Some targets like their CSRs used from one end, and some targets want them used from the other end. When computing an allocation order, simply preserve the relative ordering of CSRs that the target specifies in its allocation order. Reordering CSRs would break some targets, ARM in particular. We still place volatiles before the CSRs, providing slightly better results with different calling conventions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132680 91177308-0d34-0410-b5e6-96231b3b80d8
115 lines
3.7 KiB
C++
115 lines
3.7 KiB
C++
//===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RegisterClassInfo class which provides dynamic
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// information about target register classes. Callee saved and reserved
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// registers depends on calling conventions and other dynamic information, so
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// some things cannot be determined statically.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "RegisterClassInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
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{}
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void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
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bool Update = false;
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MF = &mf;
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// Allocate new array the first time we see a new target.
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if (MF->getTarget().getRegisterInfo() != TRI) {
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TRI = MF->getTarget().getRegisterInfo();
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RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
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Update = true;
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}
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// Does this MF have different CSRs?
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const unsigned *CSR = TRI->getCalleeSavedRegs(MF);
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if (Update || CSR != CalleeSaved) {
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// Build a CSRNum map. Every CSR alias gets an entry pointing to the last
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// overlapping CSR.
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CSRNum.clear();
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CSRNum.resize(TRI->getNumRegs(), 0);
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for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
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for (const unsigned *AS = TRI->getOverlaps(Reg);
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unsigned Alias = *AS; ++AS)
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CSRNum[Alias] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
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Update = true;
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}
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CalleeSaved = CSR;
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// Different reserved registers?
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BitVector RR = TRI->getReservedRegs(*MF);
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if (RR != Reserved)
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Update = true;
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Reserved = RR;
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// Invalidate cached information from previous function.
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if (Update)
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++Tag;
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}
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/// compute - Compute the preferred allocation order for RC with reserved
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/// registers filtered out. Volatile registers come first followed by CSR
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/// aliases ordered according to the CSR order specified by the target.
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void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
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RCInfo &RCI = RegClass[RC->getID()];
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// Raw register count, including all reserved regs.
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unsigned NumRegs = RC->getNumRegs();
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if (!RCI.Order)
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RCI.Order.reset(new unsigned[NumRegs]);
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unsigned N = 0;
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SmallVector<unsigned, 16> CSRAlias;
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// FIXME: Once targets reserve registers instead of removing them from the
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// allocation order, we can simply use begin/end here.
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TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
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TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
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for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
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unsigned PhysReg = *I;
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// Remove reserved registers from the allocation order.
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if (Reserved.test(PhysReg))
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continue;
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if (CSRNum[PhysReg])
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// PhysReg aliases a CSR, save it for later.
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CSRAlias.push_back(PhysReg);
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else
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RCI.Order[N++] = PhysReg;
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}
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RCI.NumRegs = N + CSRAlias.size();
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assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
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// CSR aliases go after the volatile registers, preserve the target's order.
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std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]);
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DEBUG({
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dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
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for (unsigned I = 0; I != N; ++I)
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dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
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dbgs() << " ]\n";
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});
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// RCI is now up-to-date.
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RCI.Tag = Tag;
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}
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