llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 04:33:05 +00:00

History

Chris Lattner f0144127b9 Rip all of the global variable lowering logic out of TargetAsmInfo. Since it is highly specific to the object file that will be generated in the end, this introduces a new TargetLoweringObjectFile interface that is implemented for each of ELF/MachO/COFF/Alpha/PIC16 and XCore. Though still is still a brutal and ugly refactoring, this is a major step towards goodness. This patch also: 1. fixes a bunch of dangling pointer problems in the PIC16 backend. 2. disables the TargetLowering copy ctor which PIC16 was accidentally using. 3. gets us closer to xcore having its own crazy target section flags and pic16 not having to shadow sections with its own objects. 4. fixes wierdness where ELF targets would set CStringSection but not CStringSection_. Factor the code better. 5. fixes some bugs in string lowering on ELF targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77294 91177308-0d34-0410-b5e6-96231b3b80d8		2009-07-28 03:13:23 +00:00
..
AsmPrinter	Rip all of the global variable lowering logic out of TargetAsmInfo. Since	2009-07-28 03:13:23 +00:00
TargetInfo	Factor commonality in triple match routines into helper template for registering	2009-07-26 05:03:33 +00:00
CMakeLists.txt
DelaySlotFiller.cpp
FPMover.cpp
Makefile
README.txt
Sparc.h	Add new helpers for registering targets.	2009-07-25 06:49:55 +00:00
Sparc.td
SparcCallingConv.td
SparcInstrFormats.td
SparcInstrInfo.cpp
SparcInstrInfo.h
SparcInstrInfo.td
SparcISelDAGToDAG.cpp
SparcISelLowering.cpp	Rip all of the global variable lowering logic out of TargetAsmInfo. Since	2009-07-28 03:13:23 +00:00
SparcISelLowering.h
SparcRegisterInfo.cpp
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetAsmInfo.cpp	Rip all of the global variable lowering logic out of TargetAsmInfo. Since	2009-07-28 03:13:23 +00:00
SparcTargetAsmInfo.h	Rip all of the global variable lowering logic out of TargetAsmInfo. Since	2009-07-28 03:13:23 +00:00
SparcTargetMachine.cpp	Add new helpers for registering targets.	2009-07-25 06:49:55 +00:00
SparcTargetMachine.h

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots