Evan Cheng d2ca813549 Correct some load / store instruction itinerary mistakes: ...

1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8

2010-10-09 01:03:04 +00:00

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Alpha

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ARM

Correct some load / store instruction itinerary mistakes:

2010-10-09 01:03:04 +00:00

Blackfin

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CBackend

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CellSPU

Zap some redundant 'ori $?, $?, 0' from SPU.

2010-10-01 09:20:01 +00:00

CPP

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Generic

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MBlaze

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Mips

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MSP430

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PIC16

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PowerPC

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PTX

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SPARC

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SystemZ

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Thumb

Try again to disable critical edge splitting in CodeGenPrepare.

2010-09-30 20:51:52 +00:00

Thumb2

Change register allocation order for ARM VFP and NEON registers to put the

2010-10-08 06:15:13 +00:00

X86

Recommit 116056, now with the missing file...

2010-10-08 19:24:18 +00:00

XCore

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thumb2-mul.ll

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