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typically cost 1 cycle) instead of shld/shrd instruction (which are typically 6 or more cycles). This also saves code space. For example, instead of emitting: rotr: mov %EAX, DWORD PTR [%ESP + 4] mov %CL, BYTE PTR [%ESP + 8] shrd %EAX, %EAX, %CL ret rotli: mov %EAX, DWORD PTR [%ESP + 4] shrd %EAX, %EAX, 27 ret Emit: rotr32: mov %CL, BYTE PTR [%ESP + 8] mov %EAX, DWORD PTR [%ESP + 4] ror %EAX, %CL ret rotli32: mov %EAX, DWORD PTR [%ESP + 4] ror %EAX, 27 ret We also emit byte rotate instructions which do not have a sh[lr]d counterpart at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19692 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
CBackend | ||
PowerPC | ||
Skeleton | ||
Sparc | ||
SparcV8 | ||
SparcV9 | ||
X86 | ||
Makefile | ||
MRegisterInfo.cpp | ||
Target.td | ||
TargetData.cpp | ||
TargetFrameInfo.cpp | ||
TargetInstrInfo.cpp | ||
TargetMachine.cpp | ||
TargetMachineRegistry.cpp | ||
TargetSchedInfo.cpp |