Tom Stellard 7dd37ae57a R600/SI: Add support for i8 and i16 private loads/stores ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199823 91177308-0d34-0410-b5e6-96231b3b80d8		2014-01-22 19:24:14 +00:00
..
AArch64	[AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or SHUFFLE_VECTOR.	2014-01-22 06:11:03 +00:00
ARM	Fix inline assembly that switches between ARM and Thumb modes	2014-01-22 18:32:35 +00:00
CPP
Generic	Remove a failing test to get the buildbots back to green.	2014-01-06 00:43:09 +00:00
Hexagon
Inputs
Mips	Fix PR18572 - llc crash during GenericScheduler::initPolicy().	2014-01-21 21:27:37 +00:00
MSP430
NVPTX	[NVPTX] Add missing patterns for div.approx with immediate denominator	2014-01-21 14:40:05 +00:00
PowerPC	Fix pointer info on PPC byval stores	2014-01-21 20:15:58 +00:00
R600	R600/SI: Add support for i8 and i16 private loads/stores	2014-01-22 19:24:14 +00:00
SPARC	[Sparc] Add support for inline assembly constraints which specify registers by their aliases.	2014-01-22 03:18:42 +00:00
SystemZ	[SystemZ] Flesh out stackrestore test (frame-11.ll)	2014-01-13 15:44:44 +00:00
Thumb	CodeGen: Stop treating vectors as aggregates	2014-01-21 22:46:46 +00:00
Thumb2	Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks	2014-01-13 18:47:54 +00:00
X86	AVX512: combining setcc and zext is wrong on AVX512	2014-01-22 12:26:19 +00:00
XCore	Fix broken CHECK lines.	2014-01-11 21:06:00 +00:00