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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239161 91177308-0d34-0410-b5e6-96231b3b80d8
158 lines
5.9 KiB
TableGen
158 lines
5.9 KiB
TableGen
//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hexagon V4 instruction classes in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//----------------------------------------------------------------------------//
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// Hexagon Instruction Flags
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//
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// *** Must match BaseInfo.h ***
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//----------------------------------------------------------------------------//
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def TypeMEMOP : IType<9>;
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def TypeNV : IType<10>;
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def TypeDUPLEX : IType<11>;
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def TypeCOMPOUND : IType<12>;
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def TypeAG_VX : IType<28>;
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def TypeAG_VM : IType<29>;
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def TypePREFIX : IType<30>;
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// Duplex Instruction Class Declaration
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//===----------------------------------------------------------------------===//
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class OpcodeDuplex {
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field bits<32> Inst = ?; // Default to an invalid insn.
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bits<4> IClass = 0; // ICLASS
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bits<13> ISubHi = 0; // Low sub-insn
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bits<13> ISubLo = 0; // High sub-insn
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let Inst{31-29} = IClass{3-1};
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let Inst{13} = IClass{0};
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let Inst{15-14} = 0;
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let Inst{28-16} = ISubHi;
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let Inst{12-0} = ISubLo;
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}
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class InstDuplex<bits<4> iClass, list<dag> pattern = [],
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string cstr = "">
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: Instruction, OpcodeDuplex {
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let Namespace = "Hexagon";
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IType Type = TypeDUPLEX; // uses slot 0,1
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let isCodeGenOnly = 1;
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let hasSideEffects = 0;
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dag OutOperandList = (outs);
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dag InOperandList = (ins);
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let IClass = iClass;
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let Constraints = cstr;
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let Itinerary = DUPLEX;
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let Size = 4;
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// SoftFail is a field the disassembler can use to provide a way for
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// instructions to not match without killing the whole decode process. It is
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// mainly used for ARM, but Tablegen expects this field to exist or it fails
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// to build the decode table.
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field bits<32> SoftFail = 0;
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// *** Must match MCTargetDesc/HexagonBaseInfo.h ***
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let TSFlags{4-0} = Type.Value;
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// Predicated instructions.
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bits<1> isPredicated = 0;
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let TSFlags{6} = isPredicated;
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bits<1> isPredicatedFalse = 0;
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let TSFlags{7} = isPredicatedFalse;
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bits<1> isPredicatedNew = 0;
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let TSFlags{8} = isPredicatedNew;
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// New-value insn helper fields.
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bits<1> isNewValue = 0;
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let TSFlags{9} = isNewValue; // New-value consumer insn.
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bits<1> hasNewValue = 0;
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let TSFlags{10} = hasNewValue; // New-value producer insn.
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bits<3> opNewValue = 0;
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let TSFlags{13-11} = opNewValue; // New-value produced operand.
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bits<1> isNVStorable = 0;
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let TSFlags{14} = isNVStorable; // Store that can become new-value store.
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bits<1> isNVStore = 0;
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let TSFlags{15} = isNVStore; // New-value store insn.
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// Immediate extender helper fields.
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bits<1> isExtendable = 0;
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let TSFlags{16} = isExtendable; // Insn may be extended.
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bits<1> isExtended = 0;
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let TSFlags{17} = isExtended; // Insn must be extended.
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bits<3> opExtendable = 0;
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let TSFlags{20-18} = opExtendable; // Which operand may be extended.
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bits<1> isExtentSigned = 0;
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let TSFlags{21} = isExtentSigned; // Signed or unsigned range.
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bits<5> opExtentBits = 0;
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let TSFlags{26-22} = opExtentBits; //Number of bits of range before extending.
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bits<2> opExtentAlign = 0;
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let TSFlags{28-27} = opExtentAlign; // Alignment exponent before extending.
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}
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//----------------------------------------------------------------------------//
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// Instruction Classes Definitions
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//----------------------------------------------------------------------------//
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//
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// NV type instructions.
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//
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class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNV>, OpcodeHexagon;
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class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0>
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: NVInst<outs, ins, asmstr, pattern, cstr, itin>;
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// Definition of Post increment new value store.
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class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
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: NVInst<outs, ins, asmstr, pattern, cstr, itin>;
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// Post increment ST Instruction.
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let mayStore = 1 in
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class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
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: NVInst<outs, ins, asmstr, pattern, cstr, itin>;
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// New-value conditional branch.
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class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: NVInst<outs, ins, asmstr, pattern, cstr>;
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let mayLoad = 1, mayStore = 1 in
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class MEMInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeMEMOP>,
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OpcodeHexagon;
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class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0>
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: MEMInst<outs, ins, asmstr, pattern, cstr, itin>;
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let isCodeGenOnly = 1 in
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class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstHexagon<outs, ins, asmstr, pattern, "", EXTENDER_tc_1_SLOT0123,
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TypePREFIX>, OpcodeHexagon;
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class SUBInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypeDUPLEX>,
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OpcodeHexagon;
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class CJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCOMPOUND>,
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OpcodeHexagon;
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