Colin LeMahieu 7e9a77a2aa [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224550 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-18 23:27:51 +00:00
..
AArch64	Update AArch64 ELF relocations to ABI 1.0	2014-11-26 10:49:18 +00:00
ARM	ARM: fix an off-by-one in the register list access	2014-12-18 16:16:53 +00:00
AsmParser	MC: AsmLexer: handle multi-character CommentStrings correctly	2014-08-14 02:51:43 +00:00
COFF	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Disassembler	[Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.	2014-12-18 23:27:51 +00:00
ELF	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Hexagon	[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.	2014-12-09 18:16:49 +00:00
MachO	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Markup
Mips	[mips][microMIPS] Implement SWP and LWP instructions	2014-12-16 14:59:10 +00:00
PowerPC	Add parsing of 'foo@local".	2014-12-17 06:23:35 +00:00
R600	R600/SI: Start implementing an assembler	2014-11-14 14:08:00 +00:00
Sparc	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
SystemZ	Exclude known and bugzilled failures from UBSan bootstrap	2014-09-17 20:17:52 +00:00
X86	[MC] Reset the MCInst in the matcher function before adding opcode/operands.	2014-12-16 18:05:28 +00:00