llvm-6502/test/CodeGen
Dale Johannesen 7f6eb639bd Use sdmem and sse_load_f64 (etc.) for the vector
form of CMPSD (etc.)  Matching a 128-bit memory
operand is wrong, the instruction uses only 64 bits
(same as ADDSD etc.)  8193553.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110491 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-07 00:33:42 +00:00
..
Alpha PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually 2010-08-01 21:13:28 +00:00
ARM Fix eabi calling convention when a 64 bit value shadows r3. 2010-08-06 15:35:32 +00:00
Blackfin
CBackend
CellSPU Make SPU backend handle insertelement and 2010-08-04 13:59:48 +00:00
CPP
Generic Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself 2010-07-27 18:02:18 +00:00
MBlaze
Mips Fix PR7174, a couple o Mips fixes: 2010-07-20 08:37:04 +00:00
MSP430
PIC16
PowerPC PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR. 2010-08-02 00:18:19 +00:00
SPARC
SystemZ
Thumb Feed the right output into FileCheck. 2010-07-16 10:58:02 +00:00
Thumb2 Many Thumb2 instructions can reference the full ARM register set (i.e., 2010-07-30 02:41:01 +00:00
X86 Use sdmem and sse_load_f64 (etc.) for the vector 2010-08-07 00:33:42 +00:00
XCore