llvm-6502/test/MC/Disassembler/AArch64
Tim Northover 6ff3ac67e0 AArch64: add BFC alias for the BFI/BFM instructions.
Unlike 32-bit ARM, AArch64 can use wzr/xzr to implement this without the need
for a separate instruction.

rdar://18679590

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236245 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-30 18:28:58 +00:00
..
a64-ignored-fields.txt
arm64-advsimd.txt
arm64-arithmetic.txt
arm64-basic-a64-undefined.txt
arm64-bitfield.txt
arm64-branch.txt
arm64-canonical-form.txt
arm64-crc32.txt
arm64-crypto.txt
arm64-invalid-logical.txt
arm64-logical.txt
arm64-memory.txt
arm64-non-apple-fmov.txt
arm64-scalar-fp.txt
arm64-system.txt
armv8.1a-lor.txt [AArch64] LORID_EL1 register must be treated as read-only 2015-04-20 16:54:37 +00:00
armv8.1a-pan.txt
armv8.1a-rdma.txt
armv8.1a-vhe.txt [AArch64] Add v8.1a "Virtualization Host Extensions" 2015-04-16 15:38:58 +00:00
basic-a64-instructions.txt AArch64: add BFC alias for the BFI/BFM instructions. 2015-04-30 18:28:58 +00:00
basic-a64-undefined.txt
basic-a64-unpredictable.txt
gicv3-regs.txt
ldp-offset-predictable.txt
ldp-postind.predictable.txt
ldp-preind.predictable.txt
lit.local.cfg
neon-instructions.txt
trace-regs.txt