Daniel Sanders 8007133f3e [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 ... Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210777 91177308-0d34-0410-b5e6-96231b3b80d8		2014-06-12 13:39:06 +00:00
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AArch64	[AArch64] Basic Sched Model for Cortex-A57.	2014-06-11 21:06:56 +00:00
ARM
CPP
Generic
Hexagon	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Inputs
Mips	[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6	2014-06-12 13:39:06 +00:00
MSP430
NVPTX
PowerPC
R600	R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*	2014-06-12 08:21:54 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	[X86] Teach how to combine AVX and AVX2 horizontal binop on packed 256-bit vectors.	2014-06-12 10:53:48 +00:00
XCore