mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-08 19:06:39 +00:00
027fdbe3ba
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
2.1 KiB
TableGen
63 lines
2.1 KiB
TableGen
//===- XCore.td - Describe the XCore Target Machine --------*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target-independent interfaces which we are implementing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "llvm/Target/Target.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "XCoreRegisterInfo.td"
|
|
include "XCoreInstrInfo.td"
|
|
include "XCoreCallingConv.td"
|
|
|
|
def XCoreInstrInfo : InstrInfo {
|
|
let TSFlagsFields = [];
|
|
let TSFlagsShifts = [];
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// XCore Subtarget features.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def FeatureXS1A
|
|
: SubtargetFeature<"xs1a", "IsXS1A", "true",
|
|
"Enable XS1A instructions">;
|
|
|
|
def FeatureXS1B
|
|
: SubtargetFeature<"xs1b", "IsXS1B", "true",
|
|
"Enable XS1B instructions">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// XCore processors supported.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class Proc<string Name, list<SubtargetFeature> Features>
|
|
: Processor<Name, NoItineraries, Features>;
|
|
|
|
def : Proc<"generic", [FeatureXS1A]>;
|
|
def : Proc<"xs1a-generic", [FeatureXS1A]>;
|
|
def : Proc<"xs1b-generic", [FeatureXS1B]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Declare the target which we are implementing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def XCore : Target {
|
|
// Pull in Instruction Info:
|
|
let InstructionSet = XCoreInstrInfo;
|
|
}
|