Evan Cheng 824a70a384 Avoid partial CPSR dependency from loop backedges. rdar://10357570 ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143145 91177308-0d34-0410-b5e6-96231b3b80d8		2011-10-27 21:21:05 +00:00
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Alpha	Change the default scheduler from Latency to ILP, since Latency	2011-10-24 17:45:02 +00:00
ARM	Avoid partial CPSR dependency from loop backedges. rdar://10357570	2011-10-27 21:21:05 +00:00
CBackend	Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported	2011-09-26 06:44:27 +00:00
CellSPU	Enable element promotion type legalization by deafault.	2011-10-16 20:31:33 +00:00
CPP
Generic	Remove the the test which checks the saving of a vector of booleans into memory.	2011-10-16 19:06:06 +00:00
MBlaze	Change the default scheduler from Latency to ILP, since Latency	2011-10-24 17:45:02 +00:00
Mips	Change the default scheduler from Latency to ILP, since Latency	2011-10-24 17:45:02 +00:00
MSP430	Remove the explicit request for "Latency" scheduling from MSP430,	2011-10-24 17:53:16 +00:00
PowerPC	Change the default scheduler from Latency to ILP, since Latency	2011-10-24 17:45:02 +00:00
PTX	Change the default scheduler from Latency to ILP, since Latency	2011-10-24 17:45:02 +00:00
SPARC
Thumb	Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...	2011-10-11 21:40:47 +00:00
Thumb2	ARM Darwin default relocation model is PIC.	2011-09-30 17:41:35 +00:00
X86	Changed test to check for correct load size instead of shift as the shift might change if optimised	2011-10-27 18:15:58 +00:00
XCore	Associate a MemOperand with LDWCP nodes introduced during ISel.	2011-09-12 14:43:23 +00:00