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https://github.com/c64scene-ar/llvm-6502.git
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1c3af779fc
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>. t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the assembly printer correctly prints the 's' suffix. Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags. Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS. Fixes ARM SBC lowering to check for live carry (potential bug). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130048 91177308-0d34-0410-b5e6-96231b3b80d8
11 lines
286 B
LLVM
11 lines
286 B
LLVM
; RUN: llc < %s -march=thumb -mattr=+thumb2 -mattr=+32bit | FileCheck %s
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define i64 @f1(i64 %a, i64 %b) {
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; CHECK: f1:
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; CHECK: subs.w r0, r0, r2
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; To test dead_carry, +32bit prevents sbc conveting to 16-bit sbcs
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; CHECK: sbc.w r1, r1, r3
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%tmp = sub i64 %a, %b
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ret i64 %tmp
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}
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