Rafael Espindola 82759c6cac Reorganize the x86 ELF relocation selection logic. ... The main differences are: * Split in 32 and 64 bit functions. * First switch on the Modifier so that we have only one non fully covered switch. * Map the fixup kind first to a x86_64 (or i386) specific enum, to make it easy to handle cases like X86::reloc_riprel_4byte_movq_load. * Switch on IsPCRel last, which reduces code duplication. Fixes pr22308. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232837 91177308-0d34-0410-b5e6-96231b3b80d8		2015-03-20 19:48:54 +00:00
..
AArch64	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
ARM	[ARM] Add support for ARMV6K subtarget (LLVM)	2015-03-17 11:55:28 +00:00
AsmParser	Add support for .ifnes psuedo-op.	2015-03-18 14:20:54 +00:00
COFF	[opaque pointer type] Add textual IR support for explicit type parameter to gep operator	2015-03-13 18:20:45 +00:00
Disassembler	Add a bunch of CHECK missing colons in tests. NFC.	2015-03-14 01:43:57 +00:00
ELF	Reorganize the x86 ELF relocation selection logic.	2015-03-20 19:48:54 +00:00
Hexagon	[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.	2014-12-09 18:16:49 +00:00
MachO	[opaque pointer type] Add textual IR support for explicit type parameter to gep operator	2015-03-13 18:20:45 +00:00
Markup
Mips	[mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.	2015-03-17 13:17:44 +00:00
PowerPC	Add support for part-word atomics for PPC	2015-03-10 20:51:07 +00:00
R600	R600/SI: Add a stub GCNTargetMachine	2015-01-06 18:00:21 +00:00
Sparc
SystemZ	[SystemZ] Support all TLS access models - MC part	2015-02-18 09:11:36 +00:00
X86	AVX-512: Added encoding tests for VPROR, VPROL instructions,	2015-03-12 07:28:41 +00:00