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The Z constraint specifies an r+r memory address, and the y modifier expands to the "r, r" in the asm string. For this initial implementation, the base register is forced to r0 (which has the special meaning of 0 for r+r addressing on PowerPC) and the full address is taken in the second register. In the future, this should be improved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167388 91177308-0d34-0410-b5e6-96231b3b80d8 |
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Analysis | ||
Archive | ||
AsmParser | ||
Bitcode | ||
CodeGen | ||
DebugInfo | ||
ExecutionEngine | ||
Linker | ||
MC | ||
Object | ||
Support | ||
TableGen | ||
Target | ||
Transforms | ||
VMCore | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
Makefile |