Chad Rosier 82c93451f3 [AArch64] Extend the number of scalar instructions supported in the AdvSIMD ... scalar integer instruction pass. This is a patch I had lying around from a few months ago. The pass is currently disabled by default, so nothing to interesting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214779 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-04 21:20:25 +00:00
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AArch64	[AArch64] Extend the number of scalar instructions supported in the AdvSIMD	2014-08-04 21:20:25 +00:00
ARM	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
CPP
Generic
Hexagon
Inputs
Mips	llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll: Add explicit -mtriple=(mips|mipsel)-linux on 4 lines.	2014-08-01 22:15:38 +00:00
MSP430
NVPTX
PowerPC	MC uses .lcomm now, so adjust.	2014-08-04 21:06:00 +00:00
R600	R600/SI: Fix extra whitespace in asm str	2014-08-03 05:27:14 +00:00
SPARC
SystemZ
Thumb	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
Thumb2	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
X86	Fix failure to invoke exception handler on Win64	2014-08-04 21:05:27 +00:00
XCore