llvm-6502/test/CodeGen
Chandler Carruth 8415f84e49 [x86] Fix a really terrible bug in the repeated 128-bin-lane shuffle
detection. It was incorrectly handling undef lanes by actually treating
an undef lane in the first 128-bit lane as a *numeric* shuffle value.

Fortunately, this almost always DTRT and disabled detecting repeated
patterns. But not always. =/ This patch introduces a much more
principled approach and fixes the miscompiles I spotted by inspection
previously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218346 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-24 01:03:57 +00:00
..
AArch64 [FastISel][AArch64] Also allow folding of sign-/zero-extend and shift-left for booleans (i1). 2014-09-22 21:08:53 +00:00
ARM Fix swift-atomics testcase 2014-09-23 23:18:01 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC [Power] Use AtomicExpandPass for fence insertion, and use lwsync where appropriate 2014-09-23 20:46:49 +00:00
R600 Revert "R600/SI: Add support for global atomic add" 2014-09-22 16:44:04 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86 [x86] Fix a really terrible bug in the repeated 128-bin-lane shuffle 2014-09-24 01:03:57 +00:00
XCore