Simon Pilgrim de3d50643c [X86][SSE] Vector integer/float conversion memory folding (cvttps2dq / cvttpd2dq) ... Fixed an issue with the (v)cvttps2dq and (v)cvttpd2dq instructions being incorrectly put in the 2 source operand folding tables instead of the 1 source operand and added the missing SSE/AVX versions. Also added missing (v)cvtps2dq and (v)cvtpd2dq instructions to the folding tables. Differential Revision: http://reviews.llvm.org/D6001 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221489 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-06 22:15:41 +00:00
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AArch64	[AArch64] Use the correct register class for ORR.	2014-11-04 22:20:07 +00:00
ARM	[RegAlloc] Remove reference to the trivial spiller in test case.	2014-11-06 19:24:18 +00:00
CPP
Generic
Hexagon	Handle ctor/init_array initialization.	2014-11-03 14:56:05 +00:00
Inputs
Mips	[mips] Tolerate the use of the %z inline asm operand modifier with non-immediates.	2014-11-06 14:25:42 +00:00
MSP430
NVPTX	[NVPTX] Add NVPTXLowerStructArgs pass	2014-11-05 18:19:30 +00:00
PowerPC
R600	R600/SI: Add testcase I forgot to commit from months ago	2014-11-05 19:01:22 +00:00
SPARC
SystemZ
Thumb	Improve logic that decides if its profitable to commute when some of the virtual registers involved have uses/defs chains connecting them to physical register. Fix up the tests that this change improves.	2014-11-05 06:43:02 +00:00
Thumb2
X86	[X86][SSE] Vector integer/float conversion memory folding (cvttps2dq / cvttpd2dq)	2014-11-06 22:15:41 +00:00
XCore