llvm-6502/2010-11-17-DAGCombineShiftBug.ll at 85fed5e0c5bc010f967948a4af6b425a5a2f2bd0 - llvm-6502 - Applefritter: Git

6502/llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-10 06:54:54 +00:00

Tanya Lattner 9684a7c128 Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first).

Added test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119749 91177308-0d34-0410-b5e6-96231b3b80d8

2010-11-18 22:06:46 +00:00

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 ; RUN: llc < %s -march=arm -mattr=+neon
 define void @lshrIllegalType(<8 x i32>* %A) nounwind {
        %tmp1 = load <8 x i32>* %A
        %tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
        store <8 x i32> %tmp2, <8 x i32>* %A
        ret void
 }