Matt Arsenault 8603a3d1c5 R600: Implement getRsqrtEstimate ...

Only do for f32 since I'm unclear on both what this is expecting
for the refinement steps in terms of accuracy, and what
f64 instruction actually provides.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225827 91177308-0d34-0410-b5e6-96231b3b80d8

2015-01-13 20:53:18 +00:00

..

AsmParser

R600/SI: Add a stub GCNTargetMachine

2015-01-06 18:00:21 +00:00

InstPrinter

R600/SI: Fix f64 inline immediates

2014-12-17 21:04:08 +00:00

MCTargetDesc

R600/SI: Use RegisterOperands to specify which operands can accept immediates

2015-01-12 19:33:18 +00:00

TargetInfo

R600/SI: Add a stub GCNTargetMachine

2015-01-06 18:00:21 +00:00

AMDGPU.h

R600/SI: Add a stub GCNTargetMachine

2015-01-06 18:00:21 +00:00

AMDGPU.td

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

AMDGPUAlwaysInlinePass.cpp

…

AMDGPUAsmPrinter.cpp

R600/SI: Remove VReg_32 register class

2015-01-07 20:59:25 +00:00

AMDGPUAsmPrinter.h

R600/SI: Emit amd_kernel_code_t header for AMDGPU environment

2014-12-02 22:00:07 +00:00

AMDGPUCallingConv.td

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AMDGPUFrameLowering.cpp

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AMDGPUFrameLowering.h

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AMDGPUInstrInfo.cpp

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

AMDGPUInstrInfo.h

…

AMDGPUInstrInfo.td

R600/SI: Add class intrinsic

2015-01-06 23:00:37 +00:00

AMDGPUInstructions.td

R600/SI: Make more unordered comparisons legal

2014-12-11 22:15:39 +00:00

AMDGPUIntrinsicInfo.cpp

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AMDGPUIntrinsicInfo.h

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AMDGPUIntrinsics.td

…

AMDGPUISelDAGToDAG.cpp

R600/SI: Use RegisterOperands to specify which operands can accept immediates

2015-01-12 19:33:18 +00:00

AMDGPUISelLowering.cpp

R600: Implement getRsqrtEstimate

2015-01-13 20:53:18 +00:00

AMDGPUISelLowering.h

R600: Implement getRsqrtEstimate

2015-01-13 20:53:18 +00:00

AMDGPUMachineFunction.cpp

…

AMDGPUMachineFunction.h

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AMDGPUMCInstLower.cpp

R600/SI: Fix f64 inline immediates

2014-12-17 21:04:08 +00:00

AMDGPUMCInstLower.h

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

AMDGPUPromoteAlloca.cpp

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AMDGPURegisterInfo.cpp

R600/SI: Enable inline assembly

2014-12-03 04:08:00 +00:00

AMDGPURegisterInfo.h

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AMDGPURegisterInfo.td

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AMDGPUSubtarget.cpp

R600/SI: Emit amd_kernel_code_t header for AMDGPU environment

2014-12-02 22:00:07 +00:00

AMDGPUSubtarget.h

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

AMDGPUTargetMachine.cpp

R600/SI: Add a stub GCNTargetMachine

2015-01-06 18:00:21 +00:00

AMDGPUTargetMachine.h

R600/SI: Add a stub GCNTargetMachine

2015-01-06 18:00:21 +00:00

AMDGPUTargetTransformInfo.cpp

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AMDILCFGStructurizer.cpp

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AMDKernelCodeT.h

R600/SI: Emit amd_kernel_code_t header for AMDGPU environment

2014-12-02 22:00:07 +00:00

CaymanInstructions.td

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CIInstructions.td

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

CMakeLists.txt

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EvergreenInstructions.td

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LLVMBuild.txt

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Makefile

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Processors.td

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

R600ClauseMergePass.cpp

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R600ControlFlowFinalizer.cpp

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R600Defines.h

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R600EmitClauseMarkers.cpp

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R600ExpandSpecialInstrs.cpp

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R600InstrFormats.td

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R600InstrInfo.cpp

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R600InstrInfo.h

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R600Instructions.td

R600/SI: Use unordered not equal instructions

2014-12-11 22:15:35 +00:00

R600Intrinsics.td

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R600ISelLowering.cpp

[SelectionDAG] Allow targets to specify legality of extloads' result

2015-01-08 00:51:32 +00:00

R600ISelLowering.h

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R600MachineFunctionInfo.cpp

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R600MachineFunctionInfo.h

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R600MachineScheduler.cpp

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R600MachineScheduler.h

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R600OptimizeVectorRegisters.cpp

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R600Packetizer.cpp

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R600RegisterInfo.cpp

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R600RegisterInfo.h

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R600RegisterInfo.td

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R600Schedule.td

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R600TextureIntrinsicsReplacer.cpp

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R700Instructions.td

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SIAnnotateControlFlow.cpp

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SIDefines.h

R600/SI: Use RegisterOperands to specify which operands can accept immediates

2015-01-12 19:33:18 +00:00

SIFixSGPRCopies.cpp

R600/SI: Remove VReg_32 register class

2015-01-07 20:59:25 +00:00

SIFixSGPRLiveRanges.cpp

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SIFoldOperands.cpp

R600/SI: Commute instructions to enable more folding opportunities

2015-01-07 22:44:19 +00:00

SIInsertWaits.cpp

R600/SI: Insert s_waitcnt before s_barrier instructions.

2015-01-06 19:52:07 +00:00

SIInstrFormats.td

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

SIInstrInfo.cpp

R600/SI: Use RegisterOperands to specify which operands can accept immediates

2015-01-12 19:33:18 +00:00

SIInstrInfo.h

R600/SI: Teach SIFoldOperands to split 64-bit constants when folding

2015-01-07 19:56:17 +00:00

SIInstrInfo.td

R600/SI: Use RegisterOperands to specify which operands can accept immediates

2015-01-12 19:33:18 +00:00

SIInstructions.td

R600/SI: Remove VReg_32 register class

2015-01-07 20:59:25 +00:00

SIIntrinsics.td

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SIISelLowering.cpp

R600/SI: Remove redundant setting expand on f64 vectors

2015-01-12 23:13:00 +00:00

SIISelLowering.h

R600/SI: Remove SIISelLowering::legalizeOperands()

2015-01-08 15:08:17 +00:00

SILoadStoreOptimizer.cpp

R600/SI: Fix live range error hidden by SIFoldOperands

2014-12-03 05:22:29 +00:00

SILowerControlFlow.cpp

R600/SI: Remove VReg_32 register class

2015-01-07 20:59:25 +00:00

SILowerI1Copies.cpp

R600/SI: Remove VReg_32 register class

2015-01-07 20:59:25 +00:00

SIMachineFunctionInfo.cpp

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SIMachineFunctionInfo.h

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SIRegisterInfo.cpp

R600/SI: Use RegisterOperands to specify which operands can accept immediates

2015-01-12 19:33:18 +00:00

SIRegisterInfo.h

R600/SI: Use RegisterOperands to specify which operands can accept immediates

2015-01-12 19:33:18 +00:00

SIRegisterInfo.td

R600/SI: Use RegisterOperands to specify which operands can accept immediates

2015-01-12 19:33:18 +00:00

SISchedule.td

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SIShrinkInstructions.cpp

R600/SI: Move continue after checking s_mov_b32.

2014-12-08 19:55:43 +00:00

SITypeRewriter.cpp

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VIInstrFormats.td

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

VIInstructions.td

R600/SI: Remove VReg_32 register class

2015-01-07 20:59:25 +00:00