llvm-6502/test/CodeGen
Colin LeMahieu 861e105e61 [Hexagon] Updating XTYPE/PRED intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228019 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-03 19:43:59 +00:00
..
AArch64 [AArch64] Prefer DUP/MOV ("CPY") to INS for vector_extract. 2015-02-02 17:55:57 +00:00
ARM Fix ARM peephole optimizeCompare to avoid optimizing unsigned cmp to 0. 2015-02-02 16:56:50 +00:00
BPF
CPP
Generic overloaded-intrinsic-name: exercise anyptr on struct 2015-01-27 20:03:08 +00:00
Hexagon [Hexagon] Updating XTYPE/PRED intrinsics. 2015-02-03 19:43:59 +00:00
Inputs
Mips
MSP430
NVPTX [NVPTX] Emit .pragma "nounroll" for loops marked with nounroll 2015-02-01 02:27:45 +00:00
PowerPC Disable 32-bit tests in tls-pic.ll until they can be repaired 2015-02-03 16:57:38 +00:00
R600 R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI 2015-02-03 17:38:12 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86 [X86][AVX2] Enabled shuffle matching for the AVX2 zero extension (128bit -> 256bit) vpmovzx* instructions. 2015-02-03 19:34:09 +00:00
XCore