llvm-6502/test/CodeGen
Bill Wendling 869d60d39d Machine sink could potentially sink instructions into a block where the physical
registers it defines then interfere with an existing preg live range.

For instance, if we had something like these machine instructions:

BB#0
  ... = imul ... EFLAGS<imp-def,dead>
  test ..., EFLAGS<imp-def>
  jcc BB#2 EFLAGS<imp-use>

BB#1
  ... ; fallthrough to BB#2

BB#2
  ... ; No code that defines EFLAGS
  jcc ... EFLAGS<imp-use>

Machine sink will come along, see that imul implicitly defines EFLAGS, but
because it's "dead", it assumes that it can move imul into BB#2. But when it
does, imul's "dead" imp-def of EFLAGS is raised from the dead (a zombie) and
messes up the condition code for the jump (and pretty much anything else which
relies upon it being correct).

The solution is to know which pregs are live going into a basic block. However,
that information isn't calculated at this point. Nor does the LiveVariables pass
take into account non-allocatable physical registers. In lieu of this, we do a
*very* conservative pass through the basic block to determine if a preg is live
coming out of it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 07:54:20 +00:00
..
Alpha
ARM Enable machine cse of instructions which define physical registers. 2010-06-02 01:08:27 +00:00
Blackfin Start function numbering at 0. 2010-04-17 16:29:15 +00:00
CBackend
CellSPU Fix handling of 'load' nodes. 2010-06-01 13:34:47 +00:00
CPP
Generic Implement expansion in type legalization for add/sub with overflow. The 2010-06-03 03:49:50 +00:00
MBlaze
Mips Start function numbering at 0. 2010-04-17 16:29:15 +00:00
MSP430 Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1), 2010-05-01 12:52:34 +00:00
PIC16
PowerPC Fix some latency computation bugs: if the use is not a machine opcode do not just return zero. 2010-05-28 23:26:21 +00:00
SPARC
SystemZ SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and 2010-05-14 22:17:42 +00:00
Thumb Enable a bunch more -regalloc=fast tests 2010-05-12 00:11:24 +00:00
Thumb2 Thumb2 RSBS instructions were being printed without the 'S' suffix. 2010-05-24 18:44:06 +00:00
X86 Machine sink could potentially sink instructions into a block where the physical 2010-06-03 07:54:20 +00:00
XCore Start function numbering at 0. 2010-04-17 16:29:15 +00:00