Dale Johannesen 86b49f8e2d Next round of earlyclobber handling. Approach the ... RA problem by expanding the live interval of an earlyclobber def back one slot. Remove overlap-earlyclobber throughout. Remove earlyclobber bits and their handling from live internals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56539 91177308-0d34-0410-b5e6-96231b3b80d8		2008-09-24 01:07:17 +00:00
..
CallingConvLower.cpp
CMakeLists.txt
DAGCombiner.cpp	Per review feedback: Only perform	2008-09-22 18:19:24 +00:00
FastISel.cpp	Arrange for FastISel code to have access to the MachineModuleInfo	2008-09-23 21:53:34 +00:00
LegalizeDAG.cpp	Fix the alignment of loads from constant pool entries when the	2008-09-22 22:40:08 +00:00
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp	Fix the alignment of loads from constant pool entries when the	2008-09-22 22:40:08 +00:00
LegalizeTypes.cpp
LegalizeTypes.h
LegalizeTypesGeneric.cpp
LegalizeVectorTypes.cpp
Makefile
ScheduleDAG.cpp
ScheduleDAGEmit.cpp	Next round of earlyclobber handling. Approach the	2008-09-24 01:07:17 +00:00
ScheduleDAGFast.cpp	Replace the LiveRegs SmallSet with a simple counter that keeps	2008-09-23 18:50:48 +00:00
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp	Replace the LiveRegs SmallSet with a simple counter that keeps	2008-09-23 18:50:48 +00:00
SelectionDAG.cpp
SelectionDAGBuild.cpp	Next round of earlyclobber handling. Approach the	2008-09-24 01:07:17 +00:00
SelectionDAGBuild.h
SelectionDAGISel.cpp	Next round of earlyclobber handling. Approach the	2008-09-24 01:07:17 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp	Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.	2008-09-24 00:05:32 +00:00