mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0bd4893a07
and switch various codegen pieces and the X86 backend over to using it. * Add some comments to SelectionDAGNodes.h * Introduce a second argument to FP_ROUND, which indicates whether the FP_ROUND changes the value of its input. If not it is safe to xform things like fp_extend(fp_round(x)) -> x. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46125 91177308-0d34-0410-b5e6-96231b3b80d8
402 lines
15 KiB
C++
402 lines
15 KiB
C++
//===-- LegalizeTypesSplit.cpp - Vector Splitting for LegalizeTypes -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements vector splitting support for LegalizeTypes. Vector
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// splitting is the act of changing a computation in an invalid vector type to
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// be a computation in multiple vectors of a smaller type. For example,
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// implementing <128 x f32> operations in terms of two <64 x f32> operations.
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//
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//===----------------------------------------------------------------------===//
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#include "LegalizeTypes.h"
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using namespace llvm;
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/// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a vector
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/// type that needs to be split. This handles non-power of two vectors.
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static void GetSplitDestVTs(MVT::ValueType InVT,
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MVT::ValueType &Lo, MVT::ValueType &Hi) {
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MVT::ValueType NewEltVT = MVT::getVectorElementType(InVT);
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unsigned NumElements = MVT::getVectorNumElements(InVT);
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if ((NumElements & (NumElements-1)) == 0) { // Simple power of two vector.
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NumElements >>= 1;
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Lo = Hi = MVT::getVectorType(NewEltVT, NumElements);
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} else { // Non-power-of-two vectors.
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unsigned NewNumElts_Lo = 1 << Log2_32(NumElements);
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unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
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Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
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Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
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}
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}
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//===----------------------------------------------------------------------===//
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// Result Vector Splitting
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//===----------------------------------------------------------------------===//
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/// SplitResult - This method is called when the specified result of the
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/// specified node is found to need vector splitting. At this point, the node
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/// may also have invalid operands or may have other results that need
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/// legalization, we just know that (at least) one result needs vector
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/// splitting.
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void DAGTypeLegalizer::SplitResult(SDNode *N, unsigned ResNo) {
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DEBUG(cerr << "Expand node result: "; N->dump(&DAG); cerr << "\n");
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SDOperand Lo, Hi;
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#if 0
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// See if the target wants to custom expand this node.
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if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
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TargetLowering::Custom) {
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// If the target wants to, allow it to lower this itself.
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if (SDNode *P = TLI.ExpandOperationResult(N, DAG)) {
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// Everything that once used N now uses P. We are guaranteed that the
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// result value types of N and the result value types of P match.
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ReplaceNodeWith(N, P);
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return;
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}
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}
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#endif
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switch (N->getOpcode()) {
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default:
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#ifndef NDEBUG
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cerr << "SplitResult #" << ResNo << ": ";
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N->dump(&DAG); cerr << "\n";
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#endif
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assert(0 && "Do not know how to split the result of this operator!");
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abort();
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case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
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case ISD::LOAD: SplitRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
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case ISD::BUILD_PAIR: SplitRes_BUILD_PAIR(N, Lo, Hi); break;
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case ISD::INSERT_VECTOR_ELT:SplitRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
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case ISD::VECTOR_SHUFFLE: SplitRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
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case ISD::BUILD_VECTOR: SplitRes_BUILD_VECTOR(N, Lo, Hi); break;
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case ISD::CONCAT_VECTORS: SplitRes_CONCAT_VECTORS(N, Lo, Hi); break;
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case ISD::BIT_CONVERT: SplitRes_BIT_CONVERT(N, Lo, Hi); break;
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case ISD::CTTZ:
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case ISD::CTLZ:
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case ISD::CTPOP:
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case ISD::FNEG:
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case ISD::FABS:
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP: SplitRes_UnOp(N, Lo, Hi); break;
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case ISD::ADD:
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case ISD::SUB:
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case ISD::MUL:
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::FDIV:
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case ISD::FPOW:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::UREM:
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case ISD::SREM:
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case ISD::FREM: SplitRes_BinOp(N, Lo, Hi); break;
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case ISD::FPOWI: SplitRes_FPOWI(N, Lo, Hi); break;
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case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
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}
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// If Lo/Hi is null, the sub-method took care of registering results etc.
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if (Lo.Val)
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SetSplitOp(SDOperand(N, ResNo), Lo, Hi);
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}
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void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
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MVT::ValueType LoVT, HiVT;
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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Lo = DAG.getNode(ISD::UNDEF, LoVT);
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Hi = DAG.getNode(ISD::UNDEF, HiVT);
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}
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void DAGTypeLegalizer::SplitRes_LOAD(LoadSDNode *LD,
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SDOperand &Lo, SDOperand &Hi) {
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MVT::ValueType LoVT, HiVT;
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GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
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SDOperand Ch = LD->getChain();
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SDOperand Ptr = LD->getBasePtr();
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const Value *SV = LD->getSrcValue();
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int SVOffset = LD->getSrcValueOffset();
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unsigned Alignment = LD->getAlignment();
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bool isVolatile = LD->isVolatile();
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Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
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unsigned IncrementSize = MVT::getSizeInBits(LoVT)/8;
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Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
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DAG.getIntPtrConstant(IncrementSize));
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SVOffset += IncrementSize;
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Alignment = MinAlign(Alignment, IncrementSize);
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Hi = DAG.getLoad(HiVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
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// Build a factor node to remember that this load is independent of the
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// other one.
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SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
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Hi.getValue(1));
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// Legalized the chain result - switch anything that used the old chain to
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// use the new one.
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ReplaceValueWith(SDOperand(LD, 1), TF);
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}
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void DAGTypeLegalizer::SplitRes_BUILD_PAIR(SDNode *N, SDOperand &Lo,
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SDOperand &Hi) {
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Lo = N->getOperand(0);
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Hi = N->getOperand(1);
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}
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void DAGTypeLegalizer::SplitRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
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SDOperand &Hi) {
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GetSplitOp(N->getOperand(0), Lo, Hi);
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unsigned Index = cast<ConstantSDNode>(N->getOperand(2))->getValue();
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SDOperand ScalarOp = N->getOperand(1);
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unsigned LoNumElts = MVT::getVectorNumElements(Lo.getValueType());
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if (Index < LoNumElts)
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Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, ScalarOp,
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N->getOperand(2));
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else
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Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, ScalarOp,
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DAG.getConstant(Index - LoNumElts, TLI.getPointerTy()));
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}
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void DAGTypeLegalizer::SplitRes_VECTOR_SHUFFLE(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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// Build the low part.
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SDOperand Mask = N->getOperand(2);
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SmallVector<SDOperand, 16> Ops;
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MVT::ValueType PtrVT = TLI.getPointerTy();
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MVT::ValueType LoVT, HiVT;
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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MVT::ValueType EltVT = MVT::getVectorElementType(LoVT);
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unsigned LoNumElts = MVT::getVectorNumElements(LoVT);
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unsigned NumElements = Mask.getNumOperands();
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// Insert all of the elements from the input that are needed. We use
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// buildvector of extractelement here because the input vectors will have
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// to be legalized, so this makes the code simpler.
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for (unsigned i = 0; i != LoNumElts; ++i) {
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unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
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SDOperand InVec = N->getOperand(0);
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if (Idx >= NumElements) {
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InVec = N->getOperand(1);
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Idx -= NumElements;
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}
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
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DAG.getConstant(Idx, PtrVT)));
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}
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Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size());
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Ops.clear();
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for (unsigned i = LoNumElts; i != NumElements; ++i) {
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unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
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SDOperand InVec = N->getOperand(0);
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if (Idx >= NumElements) {
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InVec = N->getOperand(1);
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Idx -= NumElements;
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}
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
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DAG.getConstant(Idx, PtrVT)));
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}
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Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
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}
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void DAGTypeLegalizer::SplitRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo,
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SDOperand &Hi) {
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MVT::ValueType LoVT, HiVT;
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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unsigned LoNumElts = MVT::getVectorNumElements(LoVT);
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SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
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Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
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SmallVector<SDOperand, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
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Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
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}
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void DAGTypeLegalizer::SplitRes_CONCAT_VECTORS(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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// FIXME: Handle non-power-of-two vectors?
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unsigned NumSubvectors = N->getNumOperands() / 2;
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if (NumSubvectors == 1) {
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Lo = N->getOperand(0);
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Hi = N->getOperand(1);
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return;
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}
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MVT::ValueType LoVT, HiVT;
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
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Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
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SmallVector<SDOperand, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
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Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
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}
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void DAGTypeLegalizer::SplitRes_BIT_CONVERT(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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// We know the result is a vector. The input may be either a vector or a
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// scalar value.
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SDOperand InOp = N->getOperand(0);
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if (MVT::isVector(InOp.getValueType()) &&
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MVT::getVectorNumElements(InOp.getValueType()) != 1) {
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// If this is a vector, split the vector and convert each of the pieces now.
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GetSplitOp(InOp, Lo, Hi);
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MVT::ValueType LoVT, HiVT;
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
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Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
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return;
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}
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// Lower the bit-convert to a store/load from the stack, then split the load.
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SDOperand Op = CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
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SplitRes_LOAD(cast<LoadSDNode>(Op.Val), Lo, Hi);
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}
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void DAGTypeLegalizer::SplitRes_BinOp(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
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SDOperand LHSLo, LHSHi;
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GetSplitOp(N->getOperand(0), LHSLo, LHSHi);
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SDOperand RHSLo, RHSHi;
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GetSplitOp(N->getOperand(1), RHSLo, RHSHi);
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Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
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Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
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}
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void DAGTypeLegalizer::SplitRes_UnOp(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
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// Get the dest types. This doesn't always match input types, e.g. int_to_fp.
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MVT::ValueType LoVT, HiVT;
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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GetSplitOp(N->getOperand(0), Lo, Hi);
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Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
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Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
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}
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void DAGTypeLegalizer::SplitRes_FPOWI(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
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GetSplitOp(N->getOperand(0), Lo, Hi);
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Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
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Hi = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Hi, N->getOperand(1));
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}
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void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDOperand &Lo, SDOperand &Hi){
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SDOperand LL, LH, RL, RH;
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GetSplitOp(N->getOperand(1), LL, LH);
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GetSplitOp(N->getOperand(2), RL, RH);
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SDOperand Cond = N->getOperand(0);
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Lo = DAG.getNode(ISD::SELECT, LL.getValueType(), Cond, LL, RL);
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Hi = DAG.getNode(ISD::SELECT, LH.getValueType(), Cond, LH, RH);
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}
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//===----------------------------------------------------------------------===//
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// Operand Vector Splitting
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//===----------------------------------------------------------------------===//
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/// SplitOperand - This method is called when the specified operand of the
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/// specified node is found to need vector splitting. At this point, all of the
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/// result types of the node are known to be legal, but other operands of the
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/// node may need legalization as well as the specified one.
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bool DAGTypeLegalizer::SplitOperand(SDNode *N, unsigned OpNo) {
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DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
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SDOperand Res(0, 0);
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#if 0
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if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
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TargetLowering::Custom)
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Res = TLI.LowerOperation(SDOperand(N, 0), DAG);
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#endif
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if (Res.Val == 0) {
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switch (N->getOpcode()) {
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default:
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#ifndef NDEBUG
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cerr << "SplitOperand Op #" << OpNo << ": ";
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N->dump(&DAG); cerr << "\n";
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#endif
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assert(0 && "Do not know how to split this operator's operand!");
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abort();
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case ISD::STORE: Res = SplitOp_STORE(cast<StoreSDNode>(N), OpNo); break;
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case ISD::RET: Res = SplitOp_RET(N, OpNo); break;
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}
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}
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// If the result is null, the sub-method took care of registering results etc.
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if (!Res.Val) return false;
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// If the result is N, the sub-method updated N in place. Check to see if any
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// operands are new, and if so, mark them.
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if (Res.Val == N) {
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// Mark N as new and remark N and its operands. This allows us to correctly
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// revisit N if it needs another step of promotion and allows us to visit
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// any new operands to N.
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N->setNodeId(NewNode);
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MarkNewNodes(N);
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return true;
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}
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assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
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"Invalid operand expansion");
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ReplaceValueWith(SDOperand(N, 0), Res);
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return false;
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}
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SDOperand DAGTypeLegalizer::SplitOp_STORE(StoreSDNode *N, unsigned OpNo) {
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assert(OpNo == 1 && "Can only split the stored value");
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SDOperand Ch = N->getChain();
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SDOperand Ptr = N->getBasePtr();
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int SVOffset = N->getSrcValueOffset();
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unsigned Alignment = N->getAlignment();
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bool isVol = N->isVolatile();
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SDOperand Lo, Hi;
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GetSplitOp(N->getOperand(1), Lo, Hi);
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unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
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Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, isVol, Alignment);
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// Increment the pointer to the other half.
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Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
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DAG.getIntPtrConstant(IncrementSize));
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Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
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isVol, MinAlign(Alignment, IncrementSize));
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return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
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}
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SDOperand DAGTypeLegalizer::SplitOp_RET(SDNode *N, unsigned OpNo) {
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assert(N->getNumOperands() == 3 &&"Can only handle ret of one vector so far");
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// FIXME: Returns of gcc generic vectors larger than a legal vector
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// type should be returned by reference!
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SDOperand Lo, Hi;
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GetSplitOp(N->getOperand(1), Lo, Hi);
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SDOperand Chain = N->getOperand(0); // The chain.
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SDOperand Sign = N->getOperand(2); // Signness
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return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Sign, Hi, Sign);
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}
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