mirror of
https://github.com/c64scene-ar/llvm-6502.git
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86ec7d1d07
a predecessor appearing more than once in the operand list was counted as
multiple predecessor; priority1 should be updated during scheduling;
CycleBound was updated after the node is inserted into priority queue; one
of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
.text
.align 4
.globl _f
_f:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl %eax, %edx
imull %ecx, %edx
imull %eax, %eax
imull %ecx, %ecx
addl %eax, %ecx
leal (%ecx,%edx,2), %eax
ret
It is also a slight performance win (1% - 3%) for most tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26470 91177308-0d34-0410-b5e6-96231b3b80d8
502 lines
16 KiB
C++
502 lines
16 KiB
C++
//===---- ScheduleDAGList.cpp - Implement a list scheduler for isel DAG ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Evan Cheng and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a simple two pass scheduler. The first pass attempts to push
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// backward any lengthy instructions and critical paths. The second pass packs
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// instructions into semi-optimal time slots.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include <climits>
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#include <iostream>
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#include <queue>
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#include <set>
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#include <vector>
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using namespace llvm;
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namespace {
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/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or a
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/// group of nodes flagged together.
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struct SUnit {
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SDNode *Node; // Representative node.
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std::vector<SDNode*> FlaggedNodes; // All nodes flagged to Node.
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std::set<SUnit*> Preds; // All real predecessors.
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std::set<SUnit*> ChainPreds; // All chain predecessors.
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std::set<SUnit*> Succs; // All real successors.
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std::set<SUnit*> ChainSuccs; // All chain successors.
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int NumPredsLeft; // # of preds not scheduled.
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int NumSuccsLeft; // # of succs not scheduled.
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int NumChainPredsLeft; // # of chain preds not scheduled.
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int NumChainSuccsLeft; // # of chain succs not scheduled.
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int Priority1; // Scheduling priority 1.
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int Priority2; // Scheduling priority 2.
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bool isDefNUseOperand; // Is a def&use operand.
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unsigned Latency; // Node latency.
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unsigned CycleBound; // Upper/lower cycle to be scheduled at.
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unsigned Slot; // Cycle node is scheduled at.
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SUnit *Next;
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SUnit(SDNode *node)
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: Node(node), NumPredsLeft(0), NumSuccsLeft(0),
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NumChainPredsLeft(0), NumChainSuccsLeft(0),
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Priority1(INT_MIN), Priority2(INT_MIN), isDefNUseOperand(false),
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Latency(0), CycleBound(0), Slot(0), Next(NULL) {}
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void dump(const SelectionDAG *G, bool All=true) const;
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};
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void SUnit::dump(const SelectionDAG *G, bool All) const {
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std::cerr << "SU: ";
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Node->dump(G);
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std::cerr << "\n";
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if (FlaggedNodes.size() != 0) {
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for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
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std::cerr << " ";
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FlaggedNodes[i]->dump(G);
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std::cerr << "\n";
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}
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}
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if (All) {
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std::cerr << "# preds left : " << NumPredsLeft << "\n";
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std::cerr << "# succs left : " << NumSuccsLeft << "\n";
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std::cerr << "# chain preds left : " << NumChainPredsLeft << "\n";
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std::cerr << "# chain succs left : " << NumChainSuccsLeft << "\n";
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std::cerr << "Latency : " << Latency << "\n";
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std::cerr << "Priority : " << Priority1 << " , " << Priority2 << "\n";
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if (Preds.size() != 0) {
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std::cerr << "Predecessors :\n";
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for (std::set<SUnit*>::iterator I = Preds.begin(),
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E = Preds.end(); I != E; ++I) {
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std::cerr << " ";
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(*I)->dump(G, false);
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}
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}
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if (ChainPreds.size() != 0) {
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std::cerr << "Chained Preds :\n";
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for (std::set<SUnit*>::iterator I = ChainPreds.begin(),
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E = ChainPreds.end(); I != E; ++I) {
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std::cerr << " ";
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(*I)->dump(G, false);
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}
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}
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if (Succs.size() != 0) {
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std::cerr << "Successors :\n";
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for (std::set<SUnit*>::iterator I = Succs.begin(),
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E = Succs.end(); I != E; ++I) {
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std::cerr << " ";
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(*I)->dump(G, false);
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}
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}
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if (ChainSuccs.size() != 0) {
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std::cerr << "Chained succs :\n";
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for (std::set<SUnit*>::iterator I = ChainSuccs.begin(),
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E = ChainSuccs.end(); I != E; ++I) {
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std::cerr << " ";
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(*I)->dump(G, false);
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}
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}
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}
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}
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/// Sorting functions for the Available queue.
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struct ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
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bool operator()(const SUnit* left, const SUnit* right) const {
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bool LFloater = (left ->Preds.size() == 0);
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bool RFloater = (right->Preds.size() == 0);
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int LBonus = (int)left ->isDefNUseOperand;
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int RBonus = (int)right->isDefNUseOperand;
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int LPriority1 = left ->Priority1 - LBonus;
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int RPriority1 = right->Priority1 - RBonus;
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int LPriority2 = left ->Priority2 + LBonus;
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int RPriority2 = right->Priority2 + RBonus;
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// Favor floaters (i.e. node with no non-passive predecessors):
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// e.g. MOV32ri.
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if (!LFloater && RFloater)
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return true;
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else if (LFloater == RFloater)
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if (LPriority1 > RPriority1)
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return true;
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else if (LPriority1 == RPriority1)
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if (LPriority2 < RPriority2)
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return true;
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else if (LPriority1 == RPriority1)
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if (left->CycleBound > right->CycleBound)
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return true;
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else
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return left->Node->getNodeDepth() < right->Node->getNodeDepth();
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return false;
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}
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};
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/// ScheduleDAGList - List scheduler.
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class ScheduleDAGList : public ScheduleDAG {
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private:
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// SDNode to SUnit mapping (many to one).
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std::map<SDNode*, SUnit*> SUnitMap;
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// Available queue.
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std::priority_queue<SUnit*, std::vector<SUnit*>, ls_rr_sort> Available;
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// The schedule.
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std::vector<SUnit*> Sequence;
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// Current scheduling cycle.
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unsigned CurrCycle;
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// First and last SUnit created.
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SUnit *HeadSUnit, *TailSUnit;
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public:
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ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb,
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const TargetMachine &tm)
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: ScheduleDAG(listSchedulingBURR, dag, bb, tm),
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CurrCycle(0), HeadSUnit(NULL), TailSUnit(NULL) {};
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~ScheduleDAGList() {
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SUnit *SU = HeadSUnit;
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while (SU) {
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SUnit *NextSU = SU->Next;
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delete SU;
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SU = NextSU;
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}
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}
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void Schedule();
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void dump() const;
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private:
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SUnit *NewSUnit(SDNode *N);
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void ReleasePred(SUnit *PredSU, bool isChain = false);
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void ScheduleNode(SUnit *SU);
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int CalcNodePriority(SUnit *SU);
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void CalculatePriorities();
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void ListSchedule();
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void BuildSchedUnits();
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void EmitSchedule();
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};
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} // end namespace
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/// NewSUnit - Creates a new SUnit and return a ptr to it.
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SUnit *ScheduleDAGList::NewSUnit(SDNode *N) {
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SUnit *CurrSUnit = new SUnit(N);
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if (HeadSUnit == NULL)
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HeadSUnit = CurrSUnit;
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if (TailSUnit != NULL)
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TailSUnit->Next = CurrSUnit;
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TailSUnit = CurrSUnit;
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return CurrSUnit;
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}
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/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
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/// the Available queue is the count reaches zero. Also update its cycle bound.
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void ScheduleDAGList::ReleasePred(SUnit *PredSU, bool isChain) {
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SDNode *PredNode = PredSU->Node;
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// FIXME: the distance between two nodes is not always == the predecessor's
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// latency. For example, the reader can very well read the register written
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// by the predecessor later than the issue cycle. It also depends on the
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// interrupt model (drain vs. freeze).
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PredSU->CycleBound = std::max(PredSU->CycleBound, CurrCycle + PredSU->Latency);
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if (!isChain) {
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PredSU->NumSuccsLeft--;
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PredSU->Priority1++;
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} else
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PredSU->NumChainSuccsLeft--;
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if (PredSU->NumSuccsLeft == 0 && PredSU->NumChainSuccsLeft == 0) {
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// EntryToken has to go last!
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if (PredNode->getOpcode() != ISD::EntryToken)
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Available.push(PredSU);
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} else if (PredSU->NumSuccsLeft < 0) {
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#ifndef NDEBUG
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std::cerr << "*** List scheduling failed! ***\n";
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PredSU->dump(&DAG);
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std::cerr << " has been released too many times!\n";
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assert(0);
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#endif
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}
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}
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/// ScheduleNode - Add the node to the schedule. Decrement the pending count of
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/// its predecessors. If a predecessor pending count is zero, add it to the
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/// Available queue.
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void ScheduleDAGList::ScheduleNode(SUnit *SU) {
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Sequence.push_back(SU);
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SU->Slot = CurrCycle;
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// Bottom up: release predecessors
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for (std::set<SUnit*>::iterator I1 = SU->Preds.begin(),
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E1 = SU->Preds.end(); I1 != E1; ++I1) {
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ReleasePred(*I1);
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SU->NumPredsLeft--;
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SU->Priority1--;
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}
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for (std::set<SUnit*>::iterator I2 = SU->ChainPreds.begin(),
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E2 = SU->ChainPreds.end(); I2 != E2; ++I2)
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ReleasePred(*I2, true);
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CurrCycle++;
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}
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/// isReady - True if node's lower cycle bound is less or equal to the current
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/// scheduling cycle. Always true if all nodes have uniform latency 1.
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static inline bool isReady(SUnit *SU, unsigned CurrCycle) {
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return SU->CycleBound <= CurrCycle;
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}
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/// ListSchedule - The main loop of list scheduling.
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void ScheduleDAGList::ListSchedule() {
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// Add root to Available queue
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SUnit *Root = SUnitMap[DAG.getRoot().Val];
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Available.push(Root);
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// While Available queue is not empty, grab the node with the highest
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// priority. If it is not ready put it back. Schedule the node.
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std::vector<SUnit*> NotReady;
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while (!Available.empty()) {
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SUnit *CurrNode = Available.top();
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Available.pop();
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NotReady.clear();
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while (!isReady(CurrNode, CurrCycle)) {
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NotReady.push_back(CurrNode);
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CurrNode = Available.top();
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Available.pop();
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}
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for (unsigned i = 0, e = NotReady.size(); i != e; ++i)
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Available.push(NotReady[i]);
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DEBUG(std::cerr << "*** Scheduling: ");
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DEBUG(CurrNode->dump(&DAG, false));
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ScheduleNode(CurrNode);
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}
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// Add entry node last
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if (DAG.getEntryNode().Val != DAG.getRoot().Val) {
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SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
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Entry->Slot = CurrCycle;
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Sequence.push_back(Entry);
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}
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#ifndef NDEBUG
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bool AnyNotSched = false;
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for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) {
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if (SU->NumSuccsLeft != 0 || SU->NumChainSuccsLeft != 0) {
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if (!AnyNotSched)
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std::cerr << "*** List scheduling failed! ***\n";
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SU->dump(&DAG);
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std::cerr << "has not been scheduled!\n";
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AnyNotSched = true;
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}
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}
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assert(!AnyNotSched);
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#endif
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// Reverse the order if it is bottom up.
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std::reverse(Sequence.begin(), Sequence.end());
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DEBUG(std::cerr << "*** Final schedule ***\n");
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DEBUG(dump());
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DEBUG(std::cerr << "\n");
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}
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/// CalcNodePriority - Priority1 is just the number of live range genned -
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/// number of live range killed. Priority2 is the Sethi Ullman number. It
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/// returns Priority2 since it is calculated recursively.
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/// Smaller number is the higher priority for Priority2. Reverse is true for
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/// Priority1.
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int ScheduleDAGList::CalcNodePriority(SUnit *SU) {
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if (SU->Priority2 != INT_MIN)
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return SU->Priority2;
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SU->Priority1 = SU->NumPredsLeft - SU->NumSuccsLeft;
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if (SU->Preds.size() == 0) {
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SU->Priority2 = 1;
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} else {
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int Extra = 0;
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for (std::set<SUnit*>::iterator I = SU->Preds.begin(),
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E = SU->Preds.end(); I != E; ++I) {
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SUnit *PredSU = *I;
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int PredPriority = CalcNodePriority(PredSU);
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if (PredPriority > SU->Priority2) {
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SU->Priority2 = PredPriority;
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Extra = 0;
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} else if (PredPriority == SU->Priority2)
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Extra++;
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}
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if (SU->Node->getOpcode() != ISD::TokenFactor)
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SU->Priority2 += Extra;
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else
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SU->Priority2 = (Extra == 1) ? 0 : Extra-1;
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}
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return SU->Priority2;
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}
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/// CalculatePriorities - Calculate priorities of all scheduling units.
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void ScheduleDAGList::CalculatePriorities() {
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for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) {
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// FIXME: assumes uniform latency for now.
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SU->Latency = 1;
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(void)CalcNodePriority(SU);
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DEBUG(SU->dump(&DAG));
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DEBUG(std::cerr << "\n");
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}
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}
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void ScheduleDAGList::BuildSchedUnits() {
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// Pass 1: create the SUnit's.
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for (unsigned i = 0, NC = NodeCount; i < NC; i++) {
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NodeInfo *NI = &Info[i];
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SDNode *N = NI->Node;
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if (isPassiveNode(N))
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continue;
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SUnit *SU;
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if (NI->isInGroup()) {
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if (NI != NI->Group->getBottom()) // Bottom up, so only look at bottom
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continue; // node of the NodeGroup
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SU = NewSUnit(N);
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// Find the flagged nodes.
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SDOperand FlagOp = N->getOperand(N->getNumOperands() - 1);
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SDNode *Flag = FlagOp.Val;
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unsigned ResNo = FlagOp.ResNo;
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while (Flag->getValueType(ResNo) == MVT::Flag) {
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NodeInfo *FNI = getNI(Flag);
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assert(FNI->Group == NI->Group);
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SU->FlaggedNodes.insert(SU->FlaggedNodes.begin(), Flag);
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SUnitMap[Flag] = SU;
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FlagOp = Flag->getOperand(Flag->getNumOperands() - 1);
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Flag = FlagOp.Val;
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ResNo = FlagOp.ResNo;
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}
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} else {
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SU = NewSUnit(N);
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}
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SUnitMap[N] = SU;
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}
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// Pass 2: add the preds, succs, etc.
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for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) {
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SDNode *N = SU->Node;
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NodeInfo *NI = getNI(N);
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if (NI->isInGroup()) {
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// Find all predecessors (of the group).
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NodeGroupOpIterator NGOI(NI);
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while (!NGOI.isEnd()) {
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SDOperand Op = NGOI.next();
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SDNode *OpN = Op.Val;
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MVT::ValueType VT = OpN->getValueType(Op.ResNo);
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NodeInfo *OpNI = getNI(OpN);
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if (OpNI->Group != NI->Group && !isPassiveNode(OpN)) {
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assert(VT != MVT::Flag);
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SUnit *OpSU = SUnitMap[OpN];
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if (VT == MVT::Other) {
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if (SU->ChainPreds.insert(OpSU).second)
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SU->NumChainPredsLeft++;
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if (OpSU->ChainSuccs.insert(SU).second)
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OpSU->NumChainSuccsLeft++;
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} else {
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if (SU->Preds.insert(OpSU).second)
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SU->NumPredsLeft++;
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if (OpSU->Succs.insert(SU).second)
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OpSU->NumSuccsLeft++;
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}
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}
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}
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} else {
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// Find node predecessors.
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for (unsigned j = 0, e = N->getNumOperands(); j != e; j++) {
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SDOperand Op = N->getOperand(j);
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SDNode *OpN = Op.Val;
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MVT::ValueType VT = OpN->getValueType(Op.ResNo);
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if (!isPassiveNode(OpN)) {
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assert(VT != MVT::Flag);
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SUnit *OpSU = SUnitMap[OpN];
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if (VT == MVT::Other) {
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if (SU->ChainPreds.insert(OpSU).second)
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SU->NumChainPredsLeft++;
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if (OpSU->ChainSuccs.insert(SU).second)
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OpSU->NumChainSuccsLeft++;
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} else {
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if (SU->Preds.insert(OpSU).second)
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SU->NumPredsLeft++;
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if (OpSU->Succs.insert(SU).second)
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OpSU->NumSuccsLeft++;
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if (j == 0 && TII->isTwoAddrInstr(N->getTargetOpcode()))
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OpSU->isDefNUseOperand = true;
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}
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}
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}
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}
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}
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}
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/// EmitSchedule - Emit the machine code in scheduled order.
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void ScheduleDAGList::EmitSchedule() {
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for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
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SDNode *N;
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SUnit *SU = Sequence[i];
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for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++) {
|
|
N = SU->FlaggedNodes[j];
|
|
EmitNode(getNI(N));
|
|
}
|
|
EmitNode(getNI(SU->Node));
|
|
}
|
|
}
|
|
|
|
/// dump - dump the schedule.
|
|
void ScheduleDAGList::dump() const {
|
|
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
|
|
SUnit *SU = Sequence[i];
|
|
SU->dump(&DAG, false);
|
|
}
|
|
}
|
|
|
|
/// Schedule - Schedule the DAG using list scheduling.
|
|
/// FIXME: Right now it only supports the burr (bottom up register reducing)
|
|
/// heuristic.
|
|
void ScheduleDAGList::Schedule() {
|
|
DEBUG(std::cerr << "********** List Scheduling **********\n");
|
|
|
|
// Build scheduling units.
|
|
BuildSchedUnits();
|
|
|
|
// Calculate node prirorities.
|
|
CalculatePriorities();
|
|
|
|
// Execute the actual scheduling loop.
|
|
ListSchedule();
|
|
|
|
// Emit in scheduled order
|
|
EmitSchedule();
|
|
}
|
|
|
|
llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG &DAG,
|
|
MachineBasicBlock *BB) {
|
|
return new ScheduleDAGList(DAG, BB, DAG.getTarget());
|
|
}
|