mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 03:29:22 +00:00
86ec7d1d07
a predecessor appearing more than once in the operand list was counted as
multiple predecessor; priority1 should be updated during scheduling;
CycleBound was updated after the node is inserted into priority queue; one
of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
.text
.align 4
.globl _f
_f:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl %eax, %edx
imull %ecx, %edx
imull %eax, %eax
imull %ecx, %ecx
addl %eax, %ecx
leal (%ecx,%edx,2), %eax
ret
It is also a slight performance win (1% - 3%) for most tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26470 91177308-0d34-0410-b5e6-96231b3b80d8
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| .. | ||
| SelectionDAG | ||
| AsmPrinter.cpp | ||
| BranchFolding.cpp | ||
| DwarfWriter.cpp | ||
| ELFWriter.cpp | ||
| IntrinsicLowering.cpp | ||
| LiveInterval.cpp | ||
| LiveIntervalAnalysis.cpp | ||
| LiveVariables.cpp | ||
| MachineBasicBlock.cpp | ||
| MachineCodeEmitter.cpp | ||
| MachineDebugInfo.cpp | ||
| MachineFunction.cpp | ||
| MachineInstr.cpp | ||
| Makefile | ||
| Passes.cpp | ||
| PHIElimination.cpp | ||
| PhysRegTracker.h | ||
| PrologEpilogInserter.cpp | ||
| RegAllocLinearScan.cpp | ||
| RegAllocLocal.cpp | ||
| RegAllocSimple.cpp | ||
| TwoAddressInstructionPass.cpp | ||
| UnreachableBlockElim.cpp | ||
| VirtRegMap.cpp | ||
| VirtRegMap.h | ||