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878c6281d3
The architecture doesn't really have any native v4f32 operations except v4f32->v2f64 and v2f64->v4f32 conversions, with only half of the v4f32 elements being used. Even so, using vector registers for <4 x float> and scalarising individual operations is much better than generating completely scalar code, since there's much less register pressure. It's also more efficient to do v4f32 comparisons by extending to 2 v2f64s, comparing those, then packing the result. This particularly helps with llvmpipe. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236523 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.3 KiB
LLVM
58 lines
1.3 KiB
LLVM
; Test scalar_to_vector expansion.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test v16i8.
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define <16 x i8> @f1(i8 %val) {
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; CHECK-LABEL: f1:
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; CHECK: vlvgb %v24, %r2, 0
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; CHECK: br %r14
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%ret = insertelement <16 x i8> undef, i8 %val, i32 0
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ret <16 x i8> %ret
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}
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; Test v8i16.
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define <8 x i16> @f2(i16 %val) {
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; CHECK-LABEL: f2:
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; CHECK: vlvgh %v24, %r2, 0
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; CHECK: br %r14
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%ret = insertelement <8 x i16> undef, i16 %val, i32 0
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ret <8 x i16> %ret
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}
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; Test v4i32.
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define <4 x i32> @f3(i32 %val) {
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; CHECK-LABEL: f3:
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; CHECK: vlvgf %v24, %r2, 0
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; CHECK: br %r14
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%ret = insertelement <4 x i32> undef, i32 %val, i32 0
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ret <4 x i32> %ret
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}
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; Test v2i64. Here we load %val into both halves.
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define <2 x i64> @f4(i64 %val) {
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; CHECK-LABEL: f4:
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; CHECK: vlvgp %v24, %r2, %r2
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; CHECK: br %r14
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%ret = insertelement <2 x i64> undef, i64 %val, i32 0
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ret <2 x i64> %ret
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}
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; Test v4f32, which is just a move.
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define <4 x float> @f5(float %val) {
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; CHECK-LABEL: f5:
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; CHECK: vlr %v24, %v0
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; CHECK: br %r14
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%ret = insertelement <4 x float> undef, float %val, i32 0
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ret <4 x float> %ret
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}
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; Likewise v2f64.
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define <2 x double> @f6(double %val) {
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; CHECK-LABEL: f6:
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; CHECK: vlr %v24, %v0
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; CHECK: br %r14
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%ret = insertelement <2 x double> undef, double %val, i32 0
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ret <2 x double> %ret
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}
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