Tom Stellard 87b983680c R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine() ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208429 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-09 16:42:16 +00:00
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AArch64	AArch64/ARM64: optimise vector selects & enable test	2014-05-07 14:10:27 +00:00
ARM	Attempt to pacify the bots - this commit requires asserts.	2014-05-09 16:20:53 +00:00
ARM64	[ARM64-BE] Teach fast-isel about how to set up sub-word stack arguments for big endian calls.	2014-05-08 12:53:50 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6	2014-05-09 09:46:21 +00:00
MSP430
NVPTX
PowerPC
R600	R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()	2014-05-09 16:42:16 +00:00
SPARC	Remove the -disable-cfi option.	2014-05-05 17:33:26 +00:00
SystemZ
Thumb
Thumb2
X86	Optimize shufflevector that copies an i64/f64 and zeros the rest.	2014-05-08 23:16:08 +00:00
XCore