mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 16:30:00 +00:00
7ca2a7d742
Adds code generation support for dcbtst (data cache prefetch for write) and icbt (instruction cache prefetch for read - Book E cores only). We still end up with a 'cannot select' error for the non-supported prefetch intrinsic forms. This will be fixed in a later commit. Fixes PR20692. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216339 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
729 B
LLVM
35 lines
729 B
LLVM
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; RUN: llc -mcpu=a2 < %s | FileCheck %s
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define void @test1(i8* %a, ...) nounwind {
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entry:
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call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 1)
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ret void
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; CHECK-LABEL: @test1
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; CHECK: dcbt
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}
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declare void @llvm.prefetch(i8*, i32, i32, i32)
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define void @test2(i8* %a, ...) nounwind {
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entry:
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call void @llvm.prefetch(i8* %a, i32 1, i32 3, i32 1)
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ret void
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; CHECK-LABEL: @test2
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; CHECK: dcbtst
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}
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define void @test3(i8* %a, ...) nounwind {
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entry:
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call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 0)
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ret void
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; CHECK-LABEL: @test3
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; CHECK: icbt
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}
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