Tim Northover 87e824120d ARM64: convert fp16 narrowing ISel to pseudo-instruction ... The previous attempt was fine with optimisations, but was actually rather cavalier with its types. When compiled at -O0, it produced invalid COPY MachineInstrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205422 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-02 14:38:54 +00:00
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AArch64	[AArch64] Lower SHL_PARTS, SRA_PARTS and SRL_PARTS	2014-03-27 16:28:09 +00:00
ARM	Remove duplicated DMB instructions	2014-04-02 09:03:43 +00:00
ARM64	ARM64: convert fp16 narrowing ISel to pseudo-instruction	2014-04-02 14:38:54 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Fixed issue with microMIPS JAL instruction.	2014-03-31 14:00:10 +00:00
MSP430	Mark FPB as a reserved register when needed.	2014-04-02 13:13:56 +00:00
NVPTX	Fix for PR19099 - NVPTX produces invalid symbol names.	2014-03-31 15:56:26 +00:00
PowerPC	[PowerPC] Add some missing VSX bitcast patterns	2014-04-01 19:24:27 +00:00
R600	Fix missing RUN line in test	2014-04-01 18:34:13 +00:00
SPARC
SystemZ	[SystemZ] Add support for z196 float<->unsigned conversions	2014-03-21 10:56:30 +00:00
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X86	Support segmented stacks on Win64	2014-04-01 18:34:21 +00:00
XCore