mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
87773c318f
Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
311 lines
11 KiB
LLVM
311 lines
11 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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declare <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8>, <8 x i8>)
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declare <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8>, <8 x i8>)
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define <8 x i8> @test_smax_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
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; Using registers other than v0, v1 are possible, but would be odd.
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; CHECK: test_smax_v8i8:
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%tmp1 = call <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
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; CHECK: smax v0.8b, v0.8b, v1.8b
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ret <8 x i8> %tmp1
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}
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define <8 x i8> @test_umax_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
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%tmp1 = call <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
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; CHECK: umax v0.8b, v0.8b, v1.8b
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ret <8 x i8> %tmp1
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}
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declare <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8>, <16 x i8>)
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declare <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8>, <16 x i8>)
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define <16 x i8> @test_smax_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
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; CHECK: test_smax_v16i8:
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%tmp1 = call <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
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; CHECK: smax v0.16b, v0.16b, v1.16b
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ret <16 x i8> %tmp1
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}
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define <16 x i8> @test_umax_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
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; CHECK: test_umax_v16i8:
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%tmp1 = call <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
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; CHECK: umax v0.16b, v0.16b, v1.16b
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ret <16 x i8> %tmp1
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}
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declare <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16>, <4 x i16>)
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declare <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16>, <4 x i16>)
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define <4 x i16> @test_smax_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
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; CHECK: test_smax_v4i16:
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%tmp1 = call <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
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; CHECK: smax v0.4h, v0.4h, v1.4h
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ret <4 x i16> %tmp1
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}
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define <4 x i16> @test_umax_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
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; CHECK: test_umax_v4i16:
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%tmp1 = call <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
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; CHECK: umax v0.4h, v0.4h, v1.4h
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ret <4 x i16> %tmp1
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}
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declare <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>)
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define <8 x i16> @test_smax_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
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; CHECK: test_smax_v8i16:
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%tmp1 = call <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
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; CHECK: smax v0.8h, v0.8h, v1.8h
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ret <8 x i16> %tmp1
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}
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define <8 x i16> @test_umax_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
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; CHECK: test_umax_v8i16:
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%tmp1 = call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
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; CHECK: umax v0.8h, v0.8h, v1.8h
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ret <8 x i16> %tmp1
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}
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declare <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32>, <2 x i32>)
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declare <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32>, <2 x i32>)
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define <2 x i32> @test_smax_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK: test_smax_v2i32:
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%tmp1 = call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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; CHECK: smax v0.2s, v0.2s, v1.2s
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ret <2 x i32> %tmp1
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}
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define <2 x i32> @test_umax_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK: test_umax_v2i32:
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%tmp1 = call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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; CHECK: umax v0.2s, v0.2s, v1.2s
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ret <2 x i32> %tmp1
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}
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declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>)
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define <4 x i32> @test_smax_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
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; CHECK: test_smax_v4i32:
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%tmp1 = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
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; CHECK: smax v0.4s, v0.4s, v1.4s
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ret <4 x i32> %tmp1
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}
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define <4 x i32> @test_umax_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
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; CHECK: test_umax_v4i32:
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%tmp1 = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
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; CHECK: umax v0.4s, v0.4s, v1.4s
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ret <4 x i32> %tmp1
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}
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declare <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8>, <8 x i8>)
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declare <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8>, <8 x i8>)
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define <8 x i8> @test_smin_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
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; Using registers other than v0, v1 are possible, but would be odd.
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; CHECK: test_smin_v8i8:
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%tmp1 = call <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
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; CHECK: smin v0.8b, v0.8b, v1.8b
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ret <8 x i8> %tmp1
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}
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define <8 x i8> @test_umin_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
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%tmp1 = call <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
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; CHECK: umin v0.8b, v0.8b, v1.8b
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ret <8 x i8> %tmp1
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}
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declare <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8>, <16 x i8>)
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declare <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8>, <16 x i8>)
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define <16 x i8> @test_smin_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
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; CHECK: test_smin_v16i8:
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%tmp1 = call <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
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; CHECK: smin v0.16b, v0.16b, v1.16b
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ret <16 x i8> %tmp1
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}
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define <16 x i8> @test_umin_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
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; CHECK: test_umin_v16i8:
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%tmp1 = call <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
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; CHECK: umin v0.16b, v0.16b, v1.16b
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ret <16 x i8> %tmp1
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}
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declare <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16>, <4 x i16>)
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declare <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16>, <4 x i16>)
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define <4 x i16> @test_smin_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
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; CHECK: test_smin_v4i16:
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%tmp1 = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
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; CHECK: smin v0.4h, v0.4h, v1.4h
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ret <4 x i16> %tmp1
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}
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define <4 x i16> @test_umin_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
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; CHECK: test_umin_v4i16:
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%tmp1 = call <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
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; CHECK: umin v0.4h, v0.4h, v1.4h
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ret <4 x i16> %tmp1
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}
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declare <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16>, <8 x i16>)
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define <8 x i16> @test_smin_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
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; CHECK: test_smin_v8i16:
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%tmp1 = call <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
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; CHECK: smin v0.8h, v0.8h, v1.8h
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ret <8 x i16> %tmp1
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}
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define <8 x i16> @test_umin_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
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; CHECK: test_umin_v8i16:
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%tmp1 = call <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
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; CHECK: umin v0.8h, v0.8h, v1.8h
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ret <8 x i16> %tmp1
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}
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declare <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32>, <2 x i32>)
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declare <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32>, <2 x i32>)
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define <2 x i32> @test_smin_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK: test_smin_v2i32:
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%tmp1 = call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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; CHECK: smin v0.2s, v0.2s, v1.2s
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ret <2 x i32> %tmp1
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}
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define <2 x i32> @test_umin_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK: test_umin_v2i32:
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%tmp1 = call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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; CHECK: umin v0.2s, v0.2s, v1.2s
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ret <2 x i32> %tmp1
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}
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declare <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>)
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define <4 x i32> @test_smin_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
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; CHECK: test_smin_v4i32:
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%tmp1 = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
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; CHECK: smin v0.4s, v0.4s, v1.4s
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ret <4 x i32> %tmp1
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}
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define <4 x i32> @test_umin_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
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; CHECK: test_umin_v4i32:
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%tmp1 = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
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; CHECK: umin v0.4s, v0.4s, v1.4s
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ret <4 x i32> %tmp1
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}
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declare <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float>, <2 x float>)
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declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>)
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declare <2 x double> @llvm.arm.neon.vmaxs.v2f64(<2 x double>, <2 x double>)
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define <2 x float> @test_fmax_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
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; CHECK: test_fmax_v2f32:
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%val = call <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float> %lhs, <2 x float> %rhs)
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; CHECK: fmax v0.2s, v0.2s, v1.2s
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ret <2 x float> %val
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}
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define <4 x float> @test_fmax_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
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; CHECK: test_fmax_v4f32:
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%val = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %lhs, <4 x float> %rhs)
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; CHECK: fmax v0.4s, v0.4s, v1.4s
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ret <4 x float> %val
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}
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define <2 x double> @test_fmax_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
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; CHECK: test_fmax_v2f64:
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%val = call <2 x double> @llvm.arm.neon.vmaxs.v2f64(<2 x double> %lhs, <2 x double> %rhs)
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; CHECK: fmax v0.2d, v0.2d, v1.2d
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ret <2 x double> %val
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}
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declare <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float>, <2 x float>)
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declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>)
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declare <2 x double> @llvm.arm.neon.vmins.v2f64(<2 x double>, <2 x double>)
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define <2 x float> @test_fmin_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
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; CHECK: test_fmin_v2f32:
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%val = call <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float> %lhs, <2 x float> %rhs)
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; CHECK: fmin v0.2s, v0.2s, v1.2s
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ret <2 x float> %val
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}
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define <4 x float> @test_fmin_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
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; CHECK: test_fmin_v4f32:
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%val = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %lhs, <4 x float> %rhs)
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; CHECK: fmin v0.4s, v0.4s, v1.4s
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ret <4 x float> %val
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}
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define <2 x double> @test_fmin_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
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; CHECK: test_fmin_v2f64:
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%val = call <2 x double> @llvm.arm.neon.vmins.v2f64(<2 x double> %lhs, <2 x double> %rhs)
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; CHECK: fmin v0.2d, v0.2d, v1.2d
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ret <2 x double> %val
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}
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declare <2 x float> @llvm.aarch64.neon.vmaxnm.v2f32(<2 x float>, <2 x float>)
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declare <4 x float> @llvm.aarch64.neon.vmaxnm.v4f32(<4 x float>, <4 x float>)
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declare <2 x double> @llvm.aarch64.neon.vmaxnm.v2f64(<2 x double>, <2 x double>)
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define <2 x float> @test_fmaxnm_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
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; CHECK: test_fmaxnm_v2f32:
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%val = call <2 x float> @llvm.aarch64.neon.vmaxnm.v2f32(<2 x float> %lhs, <2 x float> %rhs)
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; CHECK: fmaxnm v0.2s, v0.2s, v1.2s
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ret <2 x float> %val
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}
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define <4 x float> @test_fmaxnm_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
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; CHECK: test_fmaxnm_v4f32:
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%val = call <4 x float> @llvm.aarch64.neon.vmaxnm.v4f32(<4 x float> %lhs, <4 x float> %rhs)
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; CHECK: fmaxnm v0.4s, v0.4s, v1.4s
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ret <4 x float> %val
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}
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define <2 x double> @test_fmaxnm_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
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; CHECK: test_fmaxnm_v2f64:
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%val = call <2 x double> @llvm.aarch64.neon.vmaxnm.v2f64(<2 x double> %lhs, <2 x double> %rhs)
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; CHECK: fmaxnm v0.2d, v0.2d, v1.2d
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ret <2 x double> %val
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}
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declare <2 x float> @llvm.aarch64.neon.vminnm.v2f32(<2 x float>, <2 x float>)
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declare <4 x float> @llvm.aarch64.neon.vminnm.v4f32(<4 x float>, <4 x float>)
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declare <2 x double> @llvm.aarch64.neon.vminnm.v2f64(<2 x double>, <2 x double>)
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define <2 x float> @test_fminnm_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
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; CHECK: test_fminnm_v2f32:
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%val = call <2 x float> @llvm.aarch64.neon.vminnm.v2f32(<2 x float> %lhs, <2 x float> %rhs)
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; CHECK: fminnm v0.2s, v0.2s, v1.2s
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ret <2 x float> %val
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}
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define <4 x float> @test_fminnm_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
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; CHECK: test_fminnm_v4f32:
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%val = call <4 x float> @llvm.aarch64.neon.vminnm.v4f32(<4 x float> %lhs, <4 x float> %rhs)
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; CHECK: fminnm v0.4s, v0.4s, v1.4s
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ret <4 x float> %val
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}
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define <2 x double> @test_fminnm_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
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; CHECK: test_fminnm_v2f64:
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%val = call <2 x double> @llvm.aarch64.neon.vminnm.v2f64(<2 x double> %lhs, <2 x double> %rhs)
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; CHECK: fminnm v0.2d, v0.2d, v1.2d
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ret <2 x double> %val
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}
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