mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 00:11:00 +00:00
3fb6877cb4
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24701 91177308-0d34-0410-b5e6-96231b3b80d8
653 lines
16 KiB
TableGen
653 lines
16 KiB
TableGen
//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// PowerPC instruction formats
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class I<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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: Instruction {
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field bits<32> Inst;
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bit PPC64 = 0; // Default value, override with isPPC64
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bit VMX = 0; // Default value, override with isVMX
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let Name = "";
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let Namespace = "PPC";
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let Inst{0-5} = opcode;
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let OperandList = OL;
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let AsmString = asmstr;
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let Itinerary = itin;
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}
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// 1.7.1 I-Form
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class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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let Pattern = pattern;
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bits<24> LI;
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let Inst{6-29} = LI;
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let Inst{30} = aa;
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let Inst{31} = lk;
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}
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// 1.7.2 B-Form
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class BForm<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode, dag OL,
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string asmstr, InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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bits<3> CR;
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bits<14> BD;
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let Inst{6-10} = bo;
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let Inst{11-13} = CR;
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let Inst{14-15} = bicode;
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let Inst{16-29} = BD;
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let Inst{30} = aa;
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let Inst{31} = lk;
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}
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// 1.7.4 D-Form
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class DForm_base<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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bits<5> A;
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bits<5> B;
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bits<16> C;
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let Pattern = pattern;
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let Inst{6-10} = A;
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let Inst{11-15} = B;
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let Inst{16-31} = C;
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}
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class DForm_1<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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bits<5> A;
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bits<16> C;
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bits<5> B;
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let Pattern = pattern;
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let Inst{6-10} = A;
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let Inst{11-15} = B;
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let Inst{16-31} = C;
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}
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class DForm_2<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: DForm_base<opcode, OL, asmstr, itin, pattern>;
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class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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bits<5> A;
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bits<16> B;
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let Pattern = pattern;
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let Inst{6-10} = A;
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let Inst{11-15} = 0;
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let Inst{16-31} = B;
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}
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// Currently we make the use/def reg distinction in ISel, not tablegen
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class DForm_3<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: DForm_1<opcode, OL, asmstr, itin, pattern>;
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class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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bits<5> B;
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bits<5> A;
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bits<16> C;
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let Pattern = pattern;
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let Inst{6-10} = A;
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let Inst{11-15} = B;
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let Inst{16-31} = C;
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}
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class DForm_4_zero<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: DForm_1<opcode, OL, asmstr, itin, pattern> {
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let A = 0;
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let B = 0;
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let C = 0;
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}
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class DForm_5<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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bits<3> BF;
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bits<1> L;
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bits<5> RA;
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bits<16> I;
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let Inst{6-8} = BF;
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let Inst{9} = 0;
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let Inst{10} = L;
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let Inst{11-15} = RA;
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let Inst{16-31} = I;
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}
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class DForm_5_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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: DForm_5<opcode, OL, asmstr, itin> {
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let L = PPC64;
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}
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class DForm_6<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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: DForm_5<opcode, OL, asmstr, itin>;
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class DForm_6_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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: DForm_6<opcode, OL, asmstr, itin> {
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let L = PPC64;
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}
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class DForm_8<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: DForm_1<opcode, OL, asmstr, itin, pattern> {
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}
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class DForm_9<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: DForm_1<opcode, OL, asmstr, itin, pattern> {
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}
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// 1.7.5 DS-Form
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class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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bits<5> RST;
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bits<14> DS;
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bits<5> RA;
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let Pattern = pattern;
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let Inst{6-10} = RST;
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let Inst{11-15} = RA;
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let Inst{16-29} = DS;
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let Inst{30-31} = xo;
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}
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class DSForm_2<bits<6> opcode, bits<2> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: DSForm_1<opcode, xo, OL, asmstr, itin, pattern>;
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// 1.7.6 X-Form
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class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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bits<5> RST;
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bits<5> A;
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bits<5> B;
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let Pattern = pattern;
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bit RC = 0; // set by isDOT
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let Inst{6-10} = RST;
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let Inst{11-15} = A;
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let Inst{16-20} = B;
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let Inst{21-30} = xo;
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let Inst{31} = RC;
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}
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// This is the same as XForm_base_r3xo, but the first two operands are swapped
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// when code is emitted.
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class XForm_base_r3xo_swapped
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<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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bits<5> A;
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bits<5> RST;
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bits<5> B;
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bit RC = 0; // set by isDOT
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let Inst{6-10} = RST;
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let Inst{11-15} = A;
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let Inst{16-20} = B;
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let Inst{21-30} = xo;
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let Inst{31} = RC;
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}
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class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>;
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class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> {
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let Pattern = pattern;
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}
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class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>;
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class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> {
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let Pattern = pattern;
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}
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class XForm_11<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> {
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let B = 0;
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let Pattern = pattern;
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}
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class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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bits<3> BF;
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bits<1> L;
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bits<5> RA;
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bits<5> RB;
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let Inst{6-8} = BF;
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let Inst{9} = 0;
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let Inst{10} = L;
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let Inst{11-15} = RA;
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let Inst{16-20} = RB;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: XForm_16<opcode, xo, OL, asmstr, itin> {
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let L = PPC64;
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}
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class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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bits<3> BF;
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bits<5> FRA;
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bits<5> FRB;
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let Inst{6-8} = BF;
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let Inst{9-10} = 0;
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let Inst{11-15} = FRA;
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let Inst{16-20} = FRB;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
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}
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class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
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let A = 0;
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}
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class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
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}
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// 1.7.7 XL-Form
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class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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bits<3> CRD;
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bits<2> CRDb;
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bits<3> CRA;
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bits<2> CRAb;
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bits<3> CRB;
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bits<2> CRBb;
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let Inst{6-8} = CRD;
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let Inst{9-10} = CRDb;
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let Inst{11-13} = CRA;
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let Inst{14-15} = CRAb;
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let Inst{16-18} = CRB;
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let Inst{19-20} = CRBb;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr,
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InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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bits<5> BO;
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bits<5> BI;
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bits<2> BH;
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let Inst{6-10} = BO;
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let Inst{11-15} = BI;
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let Inst{16-18} = 0;
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let Inst{19-20} = BH;
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let Inst{21-30} = xo;
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let Inst{31} = lk;
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}
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class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
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dag OL, string asmstr, InstrItinClass itin>
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: XLForm_2<opcode, xo, lk, OL, asmstr, itin> {
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let BO = bo;
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let BI = bi;
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let BH = 0;
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}
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class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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bits<3> BF;
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bits<3> BFA;
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let Inst{6-8} = BF;
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let Inst{9-10} = 0;
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let Inst{11-13} = BFA;
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let Inst{14-15} = 0;
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let Inst{16-20} = 0;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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// 1.7.8 XFX-Form
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class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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bits<5> RT;
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bits<10> SPR;
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let Inst{6-10} = RT;
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let Inst{11} = SPR{4};
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let Inst{12} = SPR{3};
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let Inst{13} = SPR{2};
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let Inst{14} = SPR{1};
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let Inst{15} = SPR{0};
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let Inst{16} = SPR{9};
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let Inst{17} = SPR{8};
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let Inst{18} = SPR{7};
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let Inst{19} = SPR{6};
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let Inst{20} = SPR{5};
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
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dag OL, string asmstr, InstrItinClass itin>
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: XFXForm_1<opcode, xo, OL, asmstr, itin> {
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let SPR = spr;
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}
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class XFXForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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bits<5> RT;
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let Inst{6-10} = RT;
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let Inst{11-20} = 0;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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class XFXForm_5<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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bits<8> FXM;
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bits<5> ST;
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let Inst{6-10} = ST;
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let Inst{11} = 0;
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let Inst{12-19} = FXM;
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let Inst{20} = 0;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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bits<5> ST;
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bits<8> FXM;
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let Inst{6-10} = ST;
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let Inst{11} = 1;
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let Inst{12-19} = FXM;
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let Inst{20} = 0;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: XFXForm_1<opcode, xo, OL, asmstr, itin>;
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class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
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dag OL, string asmstr, InstrItinClass itin>
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: XFXForm_7<opcode, xo, OL, asmstr, itin> {
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let SPR = spr;
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}
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// 1.7.10 XS-Form
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class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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bits<5> RS;
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bits<5> A;
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bits<6> SH;
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bit RC = 0; // set by isDOT
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let Inst{6-10} = RS;
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let Inst{11-15} = A;
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let Inst{16-20} = SH{1-5};
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let Inst{21-29} = xo;
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let Inst{30} = SH{0};
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let Inst{31} = RC;
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}
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// 1.7.11 XO-Form
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class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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bits<5> RT;
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bits<5> RA;
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bits<5> RB;
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let Pattern = pattern;
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bit RC = 0; // set by isDOT
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let Inst{6-10} = RT;
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let Inst{11-15} = RA;
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let Inst{16-20} = RB;
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let Inst{21} = oe;
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let Inst{22-30} = xo;
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let Inst{31} = RC;
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}
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class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
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dag OL, string asmstr, InstrItinClass itin, list<dag> pattern>
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: XOForm_1<opcode, xo, oe, OL, asmstr, itin, pattern> {
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let RB = 0;
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}
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|
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// 1.7.12 A-Form
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class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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|
: I<opcode, OL, asmstr, itin> {
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|
bits<5> FRT;
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|
bits<5> FRA;
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bits<5> FRC;
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|
bits<5> FRB;
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|
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let Pattern = pattern;
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|
|
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bit RC = 0; // set by isDOT
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|
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let Inst{6-10} = FRT;
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let Inst{11-15} = FRA;
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let Inst{16-20} = FRB;
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let Inst{21-25} = FRC;
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let Inst{26-30} = xo;
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let Inst{31} = RC;
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|
}
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|
|
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class AForm_2<bits<6> opcode, bits<5> xo, dag OL, string asmstr,
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|
InstrItinClass itin, list<dag> pattern>
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|
: AForm_1<opcode, xo, OL, asmstr, itin, pattern> {
|
|
let FRC = 0;
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|
}
|
|
|
|
class AForm_3<bits<6> opcode, bits<5> xo, dag OL, string asmstr,
|
|
InstrItinClass itin, list<dag> pattern>
|
|
: AForm_1<opcode, xo, OL, asmstr, itin, pattern> {
|
|
let FRB = 0;
|
|
}
|
|
|
|
// 1.7.13 M-Form
|
|
class MForm_1<bits<6> opcode, dag OL, string asmstr,
|
|
InstrItinClass itin, list<dag> pattern>
|
|
: I<opcode, OL, asmstr, itin> {
|
|
bits<5> RA;
|
|
bits<5> RS;
|
|
bits<5> RB;
|
|
bits<5> MB;
|
|
bits<5> ME;
|
|
|
|
let Pattern = pattern;
|
|
|
|
bit RC = 0; // set by isDOT
|
|
|
|
let Inst{6-10} = RS;
|
|
let Inst{11-15} = RA;
|
|
let Inst{16-20} = RB;
|
|
let Inst{21-25} = MB;
|
|
let Inst{26-30} = ME;
|
|
let Inst{31} = RC;
|
|
}
|
|
|
|
class MForm_2<bits<6> opcode, dag OL, string asmstr,
|
|
InstrItinClass itin, list<dag> pattern>
|
|
: MForm_1<opcode, OL, asmstr, itin, pattern> {
|
|
}
|
|
|
|
// 1.7.14 MD-Form
|
|
class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr,
|
|
InstrItinClass itin, list<dag> pattern>
|
|
: I<opcode, OL, asmstr, itin> {
|
|
bits<5> RS;
|
|
bits<5> RA;
|
|
bits<6> SH;
|
|
bits<6> MBE;
|
|
|
|
let Pattern = pattern;
|
|
|
|
bit RC = 0; // set by isDOT
|
|
|
|
let Inst{6-10} = RS;
|
|
let Inst{11-15} = RA;
|
|
let Inst{16-20} = SH{1-5};
|
|
let Inst{21-26} = MBE;
|
|
let Inst{27-29} = xo;
|
|
let Inst{30} = SH{0};
|
|
let Inst{31} = RC;
|
|
}
|
|
|
|
// E-1 VA-Form
|
|
class VAForm_1<bits<6> xo, dag OL, string asmstr,
|
|
InstrItinClass itin, list<dag> pattern>
|
|
: I<4, OL, asmstr, itin> {
|
|
bits<5> VD;
|
|
bits<5> VA;
|
|
bits<5> VB;
|
|
bits<5> VC;
|
|
|
|
let Pattern = pattern;
|
|
|
|
let Inst{6-10} = VD;
|
|
let Inst{11-15} = VA;
|
|
let Inst{16-20} = VB;
|
|
let Inst{21-25} = VC;
|
|
let Inst{26-31} = xo;
|
|
}
|
|
|
|
// E-2 VX-Form
|
|
class VXForm_1<bits<11> xo, dag OL, string asmstr,
|
|
InstrItinClass itin, list<dag> pattern>
|
|
: I<4, OL, asmstr, itin> {
|
|
bits<5> VD;
|
|
bits<5> VA;
|
|
bits<5> VB;
|
|
|
|
let Pattern = pattern;
|
|
|
|
let Inst{6-10} = VD;
|
|
let Inst{11-15} = VA;
|
|
let Inst{16-20} = VB;
|
|
let Inst{21-31} = xo;
|
|
}
|
|
|
|
class VXForm_setzero<bits<11> xo, dag OL, string asmstr,
|
|
InstrItinClass itin, list<dag> pattern>
|
|
: VXForm_1<xo, OL, asmstr, itin, pattern> {
|
|
let VA = VD;
|
|
let VB = VD;
|
|
}
|
|
|
|
|
|
class VXForm_2<bits<11> xo, dag OL, string asmstr,
|
|
InstrItinClass itin, list<dag> pattern>
|
|
: I<4, OL, asmstr, itin> {
|
|
bits<5> VD;
|
|
bits<5> VB;
|
|
|
|
let Pattern = pattern;
|
|
|
|
let Inst{6-10} = VD;
|
|
let Inst{11-15} = 0;
|
|
let Inst{16-20} = VB;
|
|
let Inst{21-31} = xo;
|
|
}
|
|
|
|
// E-4 VXR-Form
|
|
class VXRForm_1<bits<10> xo, bit rc, dag OL, string asmstr,
|
|
InstrItinClass itin, list<dag> pattern>
|
|
: I<4, OL, asmstr, itin> {
|
|
bits<5> VD;
|
|
bits<5> VA;
|
|
bits<5> VB;
|
|
|
|
let Pattern = pattern;
|
|
|
|
let Inst{6-10} = VD;
|
|
let Inst{11-15} = VA;
|
|
let Inst{16-20} = VB;
|
|
let Inst{21} = rc;
|
|
let Inst{22-31} = xo;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
def NoItin : InstrItinClass;
|
|
class Pseudo<dag OL, string asmstr, list<dag> pattern>
|
|
: I<0, OL, asmstr, NoItin> {
|
|
let PPC64 = 0;
|
|
let VMX = 0;
|
|
let Pattern = pattern;
|
|
let Inst{31-0} = 0;
|
|
}
|