Chad Rosier dc9205d9c2 Add support for ARM halfword load/stores and signed byte loads with negative ... offsets. rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8		2011-11-14 04:09:28 +00:00
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Analysis	Don't forget to check FlagNW when determining whether an AddRecExpr will wrap	2011-11-09 07:11:37 +00:00
Archive
Assembler
Bindings/Ocaml
Bitcode
BugPoint
CodeGen	Add support for ARM halfword load/stores and signed byte loads with negative	2011-11-14 04:09:28 +00:00
DebugInfo	The dwarf standard says that the only differences between a out-of-line	2011-11-12 01:57:54 +00:00
ExecutionEngine
Feature
Integer
lib
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MC	ARM optional size suffix for VLDR/VSTR syntax.	2011-11-11 23:34:43 +00:00
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TableGen
Transforms	Don't try to loop on iterators that are potentially invalidated inside the loop. Fixes PR11361!	2011-11-12 03:09:12 +00:00
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CMakeLists.txt	build/cmake: Change to require Python be available.	2011-11-04 23:04:05 +00:00
lit.cfg	Update lit's list of tools.	2011-11-05 16:20:52 +00:00
lit.site.cfg.in
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