Bob Wilson 7122ba7efb Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits. ...

LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned.  Radar 8489376.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115047 91177308-0d34-0410-b5e6-96231b3b80d8

2010-09-29 17:54:10 +00:00

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Alpha

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ARM

Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.

2010-09-29 17:54:10 +00:00

Blackfin

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CBackend

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CellSPU

Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.

2010-09-16 12:29:33 +00:00

CPP

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Generic

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MBlaze

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Mips

Enable machine sinking critical edge splitting. e.g.

2010-09-20 22:52:00 +00:00

MSP430

CombinerAA is now reordering these stores.

2010-09-20 20:56:29 +00:00

PIC16

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PowerPC

the latest assembler that runs on powerpc 10.4 machines doesn't

2010-09-27 06:44:54 +00:00

PTX

Add test case for PTX ret instruction

2010-09-25 07:49:54 +00:00

SPARC

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SystemZ

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Thumb

Revert "Disable codegen prepare critical edge splitting. Machine instruction passes now"

2010-09-27 18:43:48 +00:00

Thumb2

Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes

2010-09-21 22:51:46 +00:00

X86

And remove r114997's test.

2010-09-28 23:24:18 +00:00

XCore

Enable machine sinking critical edge splitting. e.g.

2010-09-20 22:52:00 +00:00

thumb2-mul.ll

Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes

2010-09-21 22:51:46 +00:00