Evan Cheng 3144687df7 - Allow target to specify when is register pressure "too high". In most cases, ... it's too late to start backing off aggressive latency scheduling when most of the registers are in use so the threshold should be a bit tighter. - Correctly handle live out's and extract_subreg etc. - Enable register pressure aware scheduling by default for hybrid scheduler. For ARM, this is almost always a win on # of instructions. It's runtime neutral for most of the tests. But for some kernels with high register pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by 54 and sped up by 20%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8		2010-07-23 22:39:59 +00:00
..
Alpha
ARM	- Allow target to specify when is register pressure "too high". In most cases,	2010-07-23 22:39:59 +00:00
Blackfin	Remove TargetInstrInfo::copyRegToReg entirely.	2010-07-11 17:01:17 +00:00
CBackend
CellSPU	Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.	2010-07-16 04:45:42 +00:00
CPP
Generic
MBlaze
Mips	Fix PR7174, a couple o Mips fixes:	2010-07-20 08:37:04 +00:00
MSP430
PIC16
PowerPC	Consider this function:	2010-07-16 22:51:10 +00:00
SPARC
SystemZ
Thumb	Feed the right output into FileCheck.	2010-07-16 10:58:02 +00:00
Thumb2	update tests for smarter BIC usage	2010-07-20 16:16:48 +00:00
X86	Use the proper type for shift counts. This fixes a bootstrap error.	2010-07-23 21:08:12 +00:00
XCore