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https://github.com/c64scene-ar/llvm-6502.git
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67b17f9ff8
Some shufflevectors are currently being incorrectly lowered in the AArch32 backend as the existing checks for detecting the NEON operations from the shufflevector instruction expects the shuffle mask and the vector operands to be of the same length. This is not always the case as the mask may be twice as long as the operand; here only the lower half of the shufflemask gets checked, so provided the lower half of the shufflemask looks like a vector transpose (or even is just all -1 for undef) then the intrinsics may get incorrectly lowered into a vector transpose (VTRN) instruction. This patch fixes this by accommodating for both cases and adds regression tests. Differential Revision: http://reviews.llvm.org/D11407 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243103 91177308-0d34-0410-b5e6-96231b3b80d8
231 lines
8.5 KiB
LLVM
231 lines
8.5 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: test_vextd:
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;CHECK: vext
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
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ret <8 x i8> %tmp3
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}
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define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: test_vextRd:
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;CHECK: vext
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
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ret <8 x i8> %tmp3
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}
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define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: test_vextq:
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;CHECK: vext
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
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ret <16 x i8> %tmp3
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}
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define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: test_vextRq:
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;CHECK: vext
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
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ret <16 x i8> %tmp3
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}
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define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: test_vextd16:
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;CHECK: vext
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
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ret <4 x i16> %tmp3
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}
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define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: test_vextq32:
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;CHECK: vext
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = load <4 x i32>, <4 x i32>* %B
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%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
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ret <4 x i32> %tmp3
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}
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; Undef shuffle indices should not prevent matching to VEXT:
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define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: test_vextd_undef:
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;CHECK: vext
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10>
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ret <8 x i8> %tmp3
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}
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define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: test_vextRq_undef:
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;CHECK: vext
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6>
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ret <16 x i8> %tmp3
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}
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define <16 x i8> @test_vextq_undef_op2(<16 x i8> %a) nounwind {
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;CHECK-LABEL: test_vextq_undef_op2:
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;CHECK: vext
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entry:
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%tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
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ret <16 x i8> %tmp1
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}
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define <8 x i8> @test_vextd_undef_op2(<8 x i8> %a) nounwind {
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;CHECK-LABEL: test_vextd_undef_op2:
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;CHECK: vext
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entry:
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%tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
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ret <8 x i8> %tmp1
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}
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define <16 x i8> @test_vextq_undef_op2_undef(<16 x i8> %a) nounwind {
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;CHECK-LABEL: test_vextq_undef_op2_undef:
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;CHECK: vext
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entry:
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%tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
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ret <16 x i8> %tmp1
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}
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define <8 x i8> @test_vextd_undef_op2_undef(<8 x i8> %a) nounwind {
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;CHECK-LABEL: test_vextd_undef_op2_undef:
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;CHECK: vext
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entry:
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%tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 1>
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ret <8 x i8> %tmp1
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}
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; Tests for ReconstructShuffle function. Indices have to be carefully
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; chosen to reach lowering phase as a BUILD_VECTOR.
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; One vector needs vext, the other can be handled by extract_subvector
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; Also checks interleaving of sources is handled correctly.
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; Essence: a vext is used on %A and something saner than stack load/store for final result.
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define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: test_interleaved:
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;CHECK: vext.16
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;CHECK-NOT: vext.16
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;CHECK: vzip.16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 3, i32 8, i32 5, i32 9>
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ret <4 x i16> %tmp3
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}
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; An undef in the shuffle list should still be optimizable
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define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: test_undef:
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;CHECK: vzip.16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>
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ret <4 x i16> %tmp3
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}
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; We should ignore a build_vector with more than two sources.
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; Use illegal <32 x i16> type to produce such a shuffle after legalizing types.
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; Try to look for fallback to by-element inserts.
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define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind {
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;CHECK-LABEL: test_multisource:
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;CHECK: vmov.16 [[REG:d[0-9]+]][0]
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;CHECK: vmov.16 [[REG]][1]
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;CHECK: vmov.16 [[REG]][2]
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;CHECK: vmov.16 [[REG]][3]
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%tmp1 = load <32 x i16>, <32 x i16>* %B
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%tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <4 x i32> <i32 0, i32 8, i32 16, i32 24>
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ret <4 x i16> %tmp2
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}
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; We don't handle shuffles using more than half of a 128-bit vector.
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; Again, test for fallback to by-element inserts.
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define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
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;CHECK-LABEL: test_largespan:
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;CHECK: vmov.16 [[REG:d[0-9]+]][0]
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;CHECK: vmov.16 [[REG]][1]
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;CHECK: vmov.16 [[REG]][2]
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;CHECK: vmov.16 [[REG]][3]
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%tmp1 = load <8 x i16>, <8 x i16>* %B
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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ret <4 x i16> %tmp2
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}
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; The actual shuffle code only handles some cases, make sure we check
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; this rather than blindly emitting a VECTOR_SHUFFLE (infinite
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; lowering loop can result otherwise).
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define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: test_illegal:
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;CHECK: vmov.16 [[REG:d[0-9]+]][0]
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;CHECK: vmov.16 [[REG]][1]
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;CHECK: vmov.16 [[REG]][2]
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;CHECK: vmov.16 [[REG]][3]
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;CHECK: vmov.16 [[REG2:d[0-9]+]][0]
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;CHECK: vmov.16 [[REG2]][1]
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;CHECK: vmov.16 [[REG2]][2]
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;CHECK: vmov.16 [[REG2]][3]
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9>
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ret <8 x i16> %tmp3
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}
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; PR11129
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; Make sure this doesn't crash
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define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
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; CHECK-LABEL: test_elem_mismatch:
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; CHECK: vstr
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%tmp0 = load <2 x i64>, <2 x i64>* %src, align 16
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%tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
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%tmp2 = extractelement <4 x i32> %tmp1, i32 0
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%tmp3 = extractelement <4 x i32> %tmp1, i32 2
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%tmp4 = trunc i32 %tmp2 to i16
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%tmp5 = trunc i32 %tmp3 to i16
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%tmp6 = insertelement <4 x i16> undef, i16 %tmp4, i32 0
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%tmp7 = insertelement <4 x i16> %tmp6, i16 %tmp5, i32 1
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store <4 x i16> %tmp7, <4 x i16>* %dest, align 4
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ret void
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}
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define <4 x i32> @test_reverse_and_extract(<2 x i32>* %A) {
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entry:
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; CHECK-LABEL: test_reverse_and_extract
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; CHECK-NOT: vtrn
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; CHECK: vrev
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; CHECK: vext
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 0>
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ret <4 x i32> %0
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}
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define <4 x i32> @test_dup_and_extract(<2 x i32>* %A) {
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entry:
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; CHECK-LABEL: test_dup_and_extract
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; CHECK-NOT: vtrn
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; CHECK: vdup
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; CHECK: vext
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
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ret <4 x i32> %0
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}
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define <4 x i32> @test_zip_and_extract(<2 x i32>* %A) {
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entry:
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; CHECK-LABEL: test_zip_and_extract
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; CHECK: vzip
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; CHECK: vext
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 1>
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ret <4 x i32> %0
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}
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