mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-25 14:30:32 +00:00
29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
156 lines
3.9 KiB
LLVM
156 lines
3.9 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone | FileCheck %s
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define void @branch1() nounwind uwtable ssp {
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%x = alloca i32, align 4
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store i32 0, i32* %x, align 4
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%1 = load i32* %x, align 4
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%2 = icmp ne i32 %1, 0
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br i1 %2, label %3, label %4
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; <label>:3 ; preds = %0
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br label %4
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; <label>:4 ; preds = %3, %0
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ret void
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}
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define void @branch2() nounwind uwtable ssp {
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%1 = alloca i32, align 4
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%x = alloca i32, align 4
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%y = alloca i32, align 4
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%z = alloca i32, align 4
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store i32 0, i32* %1
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store i32 1, i32* %y, align 4
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store i32 1, i32* %x, align 4
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store i32 0, i32* %z, align 4
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%2 = load i32* %x, align 4
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%3 = icmp ne i32 %2, 0
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br i1 %3, label %4, label %5
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; <label>:4 ; preds = %0
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store i32 0, i32* %1
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br label %14
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; <label>:5 ; preds = %0
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%6 = load i32* %y, align 4
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%7 = icmp ne i32 %6, 0
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br i1 %7, label %8, label %13
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; <label>:8 ; preds = %5
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%9 = load i32* %z, align 4
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%10 = icmp ne i32 %9, 0
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br i1 %10, label %11, label %12
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; <label>:11 ; preds = %8
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store i32 1, i32* %1
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br label %14
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; <label>:12 ; preds = %8
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store i32 0, i32* %1
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br label %14
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; <label>:13 ; preds = %5
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br label %14
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; <label>:14 ; preds = %4, %11, %12, %13
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%15 = load i32* %1
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ret void
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}
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define void @true_() nounwind uwtable ssp {
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; CHECK: @true_
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; CHECK: b LBB2_1
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br i1 true, label %1, label %2
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; <label>:1
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; CHECK: LBB2_1
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br label %2
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; <label>:2
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ret void
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}
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define void @false_() nounwind uwtable ssp {
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; CHECK: @false_
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; CHECK: b LBB3_2
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br i1 false, label %1, label %2
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; <label>:1
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br label %2
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; <label>:2
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; CHECK: LBB3_2
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ret void
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}
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define zeroext i8 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) {
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entry:
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%a.addr = alloca i8, align 1
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%b.addr = alloca i16, align 2
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%c.addr = alloca i32, align 4
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%d.addr = alloca i64, align 8
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store i8 %a, i8* %a.addr, align 1
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store i16 %b, i16* %b.addr, align 2
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store i32 %c, i32* %c.addr, align 4
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store i64 %d, i64* %d.addr, align 8
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%0 = load i16* %b.addr, align 2
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; CHECK: and w0, w0, #0x1
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; CHECK: subs w0, w0, #0
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; CHECK: b.eq LBB4_2
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%conv = trunc i16 %0 to i1
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br i1 %conv, label %if.then, label %if.end
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if.then: ; preds = %entry
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call void @foo1()
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br label %if.end
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if.end: ; preds = %if.then, %entry
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%1 = load i32* %c.addr, align 4
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; CHECK: and w[[REG:[0-9]+]], w{{[0-9]+}}, #0x1
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; CHECK: subs w{{[0-9]+}}, w[[REG]], #0
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; CHECK: b.eq LBB4_4
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%conv1 = trunc i32 %1 to i1
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br i1 %conv1, label %if.then3, label %if.end4
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if.then3: ; preds = %if.end
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call void @foo1()
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br label %if.end4
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if.end4: ; preds = %if.then3, %if.end
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%2 = load i64* %d.addr, align 8
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; CHECK: subs w{{[0-9]+}}, w{{[0-9]+}}, #0
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; CHECK: b.eq LBB4_6
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%conv5 = trunc i64 %2 to i1
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br i1 %conv5, label %if.then7, label %if.end8
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if.then7: ; preds = %if.end4
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call void @foo1()
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br label %if.end8
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if.end8: ; preds = %if.then7, %if.end4
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%3 = load i8* %a.addr, align 1
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ret i8 %3
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}
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declare void @foo1()
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; rdar://15174028
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define i32 @trunc64(i64 %foo) nounwind {
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; CHECK: trunc64
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; CHECK: orr [[REG:x[0-9]+]], xzr, #0x1
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; CHECK: and [[REG2:x[0-9]+]], x0, [[REG]]
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; CHECK: mov x[[REG3:[0-9]+]], [[REG2]]
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; CHECK: and [[REG4:w[0-9]+]], w[[REG3]], #0x1
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; CHECK: subs {{w[0-9]+}}, [[REG4]], #0
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; CHECK: b.eq LBB5_2
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%a = and i64 %foo, 1
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%b = trunc i64 %a to i1
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br i1 %b, label %if.then, label %if.else
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if.then:
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ret i32 1
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if.else:
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ret i32 0
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}
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