mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-29 13:29:28 +00:00
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
443 lines
9.8 KiB
LLVM
443 lines
9.8 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone | FileCheck %s
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;; Test various conversions.
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define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
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entry:
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; CHECK: trunc_
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; CHECK: sub sp, sp, #16
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; CHECK: strb w0, [sp, #15]
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; CHECK: strh w1, [sp, #12]
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; CHECK: str w2, [sp, #8]
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; CHECK: str x3, [sp]
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; CHECK: ldr x3, [sp]
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; CHECK: mov x0, x3
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; CHECK: str w0, [sp, #8]
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; CHECK: ldr w0, [sp, #8]
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; CHECK: strh w0, [sp, #12]
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; CHECK: ldrh w0, [sp, #12]
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; CHECK: strb w0, [sp, #15]
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; CHECK: ldrb w0, [sp, #15]
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; CHECK: uxtb w0, w0
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; CHECK: add sp, sp, #16
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; CHECK: ret
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%a.addr = alloca i8, align 1
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%b.addr = alloca i16, align 2
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%c.addr = alloca i32, align 4
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%d.addr = alloca i64, align 8
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store i8 %a, i8* %a.addr, align 1
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store i16 %b, i16* %b.addr, align 2
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store i32 %c, i32* %c.addr, align 4
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store i64 %d, i64* %d.addr, align 8
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%tmp = load i64* %d.addr, align 8
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%conv = trunc i64 %tmp to i32
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store i32 %conv, i32* %c.addr, align 4
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%tmp1 = load i32* %c.addr, align 4
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%conv2 = trunc i32 %tmp1 to i16
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store i16 %conv2, i16* %b.addr, align 2
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%tmp3 = load i16* %b.addr, align 2
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%conv4 = trunc i16 %tmp3 to i8
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store i8 %conv4, i8* %a.addr, align 1
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%tmp5 = load i8* %a.addr, align 1
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%conv6 = zext i8 %tmp5 to i32
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ret i32 %conv6
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}
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define i64 @zext_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
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entry:
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; CHECK: zext_
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; CHECK: sub sp, sp, #16
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; CHECK: strb w0, [sp, #15]
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; CHECK: strh w1, [sp, #12]
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; CHECK: str w2, [sp, #8]
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; CHECK: str x3, [sp]
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; CHECK: ldrb w0, [sp, #15]
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; CHECK: uxtb w0, w0
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; CHECK: strh w0, [sp, #12]
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; CHECK: ldrh w0, [sp, #12]
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; CHECK: uxth w0, w0
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; CHECK: str w0, [sp, #8]
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; CHECK: ldr w0, [sp, #8]
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; CHECK: mov x3, x0
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; CHECK: ubfx x3, x3, #0, #32
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; CHECK: str x3, [sp]
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; CHECK: ldr x0, [sp]
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; CHECK: ret
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%a.addr = alloca i8, align 1
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%b.addr = alloca i16, align 2
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%c.addr = alloca i32, align 4
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%d.addr = alloca i64, align 8
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store i8 %a, i8* %a.addr, align 1
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store i16 %b, i16* %b.addr, align 2
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store i32 %c, i32* %c.addr, align 4
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store i64 %d, i64* %d.addr, align 8
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%tmp = load i8* %a.addr, align 1
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%conv = zext i8 %tmp to i16
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store i16 %conv, i16* %b.addr, align 2
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%tmp1 = load i16* %b.addr, align 2
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%conv2 = zext i16 %tmp1 to i32
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store i32 %conv2, i32* %c.addr, align 4
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%tmp3 = load i32* %c.addr, align 4
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%conv4 = zext i32 %tmp3 to i64
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store i64 %conv4, i64* %d.addr, align 8
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%tmp5 = load i64* %d.addr, align 8
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ret i64 %tmp5
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}
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define i32 @zext_i1_i32(i1 zeroext %a) nounwind ssp {
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entry:
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; CHECK: @zext_i1_i32
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; CHECK: and w0, w0, #0x1
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%conv = zext i1 %a to i32
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ret i32 %conv;
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}
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define i64 @zext_i1_i64(i1 zeroext %a) nounwind ssp {
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entry:
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; CHECK: @zext_i1_i64
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; CHECK: and w0, w0, #0x1
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%conv = zext i1 %a to i64
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ret i64 %conv;
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}
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define i64 @sext_(i8 signext %a, i16 signext %b, i32 %c, i64 %d) nounwind ssp {
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entry:
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; CHECK: sext_
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; CHECK: sub sp, sp, #16
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; CHECK: strb w0, [sp, #15]
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; CHECK: strh w1, [sp, #12]
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; CHECK: str w2, [sp, #8]
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; CHECK: str x3, [sp]
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; CHECK: ldrb w0, [sp, #15]
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; CHECK: sxtb w0, w0
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; CHECK: strh w0, [sp, #12]
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; CHECK: ldrh w0, [sp, #12]
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; CHECK: sxth w0, w0
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; CHECK: str w0, [sp, #8]
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; CHECK: ldr w0, [sp, #8]
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; CHECK: mov x3, x0
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; CHECK: sxtw x3, w3
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; CHECK: str x3, [sp]
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; CHECK: ldr x0, [sp]
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; CHECK: ret
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%a.addr = alloca i8, align 1
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%b.addr = alloca i16, align 2
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%c.addr = alloca i32, align 4
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%d.addr = alloca i64, align 8
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store i8 %a, i8* %a.addr, align 1
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store i16 %b, i16* %b.addr, align 2
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store i32 %c, i32* %c.addr, align 4
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store i64 %d, i64* %d.addr, align 8
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%tmp = load i8* %a.addr, align 1
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%conv = sext i8 %tmp to i16
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store i16 %conv, i16* %b.addr, align 2
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%tmp1 = load i16* %b.addr, align 2
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%conv2 = sext i16 %tmp1 to i32
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store i32 %conv2, i32* %c.addr, align 4
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%tmp3 = load i32* %c.addr, align 4
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%conv4 = sext i32 %tmp3 to i64
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store i64 %conv4, i64* %d.addr, align 8
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%tmp5 = load i64* %d.addr, align 8
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ret i64 %tmp5
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}
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; Test sext i8 to i64
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define zeroext i64 @sext_i8_i64(i8 zeroext %in) {
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; CHECK-LABEL: sext_i8_i64:
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; CHECK: mov x[[TMP:[0-9]+]], x0
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; CHECK: sxtb x0, w[[TMP]]
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%big = sext i8 %in to i64
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ret i64 %big
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}
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define zeroext i64 @sext_i16_i64(i16 zeroext %in) {
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; CHECK-LABEL: sext_i16_i64:
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; CHECK: mov x[[TMP:[0-9]+]], x0
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; CHECK: sxth x0, w[[TMP]]
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%big = sext i16 %in to i64
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ret i64 %big
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}
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; Test sext i1 to i32
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define i32 @sext_i1_i32(i1 signext %a) nounwind ssp {
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entry:
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; CHECK: sext_i1_i32
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; CHECK: sbfx w0, w0, #0, #1
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%conv = sext i1 %a to i32
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ret i32 %conv
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}
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; Test sext i1 to i16
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define signext i16 @sext_i1_i16(i1 %a) nounwind ssp {
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entry:
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; CHECK: sext_i1_i16
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; CHECK: sbfx w0, w0, #0, #1
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%conv = sext i1 %a to i16
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ret i16 %conv
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}
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; Test sext i1 to i8
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define signext i8 @sext_i1_i8(i1 %a) nounwind ssp {
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entry:
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; CHECK: sext_i1_i8
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; CHECK: sbfx w0, w0, #0, #1
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%conv = sext i1 %a to i8
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ret i8 %conv
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}
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; Test fpext
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define double @fpext_(float %a) nounwind ssp {
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entry:
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; CHECK: fpext_
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; CHECK: fcvt d0, s0
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%conv = fpext float %a to double
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ret double %conv
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}
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; Test fptrunc
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define float @fptrunc_(double %a) nounwind ssp {
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entry:
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; CHECK: fptrunc_
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; CHECK: fcvt s0, d0
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%conv = fptrunc double %a to float
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ret float %conv
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}
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; Test fptosi
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define i32 @fptosi_ws(float %a) nounwind ssp {
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entry:
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; CHECK: fptosi_ws
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; CHECK: fcvtzs w0, s0
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%conv = fptosi float %a to i32
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ret i32 %conv
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}
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; Test fptosi
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define i32 @fptosi_wd(double %a) nounwind ssp {
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entry:
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; CHECK: fptosi_wd
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; CHECK: fcvtzs w0, d0
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%conv = fptosi double %a to i32
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ret i32 %conv
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}
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; Test fptoui
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define i32 @fptoui_ws(float %a) nounwind ssp {
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entry:
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; CHECK: fptoui_ws
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; CHECK: fcvtzu w0, s0
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%conv = fptoui float %a to i32
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ret i32 %conv
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}
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; Test fptoui
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define i32 @fptoui_wd(double %a) nounwind ssp {
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entry:
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; CHECK: fptoui_wd
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; CHECK: fcvtzu w0, d0
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%conv = fptoui double %a to i32
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ret i32 %conv
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}
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; Test sitofp
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define float @sitofp_sw_i1(i1 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sw_i1
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; CHECK: sbfx w0, w0, #0, #1
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; CHECK: scvtf s0, w0
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%conv = sitofp i1 %a to float
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ret float %conv
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}
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; Test sitofp
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define float @sitofp_sw_i8(i8 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sw_i8
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; CHECK: sxtb w0, w0
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; CHECK: scvtf s0, w0
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%conv = sitofp i8 %a to float
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ret float %conv
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}
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; Test sitofp
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define float @sitofp_sw_i16(i16 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sw_i16
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; CHECK: sxth w0, w0
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; CHECK: scvtf s0, w0
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%conv = sitofp i16 %a to float
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ret float %conv
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}
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; Test sitofp
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define float @sitofp_sw(i32 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sw
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; CHECK: scvtf s0, w0
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%conv = sitofp i32 %a to float
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ret float %conv
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}
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; Test sitofp
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define float @sitofp_sx(i64 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sx
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; CHECK: scvtf s0, x0
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%conv = sitofp i64 %a to float
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ret float %conv
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}
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; Test sitofp
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define double @sitofp_dw(i32 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_dw
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; CHECK: scvtf d0, w0
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%conv = sitofp i32 %a to double
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ret double %conv
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}
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; Test sitofp
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define double @sitofp_dx(i64 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_dx
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; CHECK: scvtf d0, x0
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%conv = sitofp i64 %a to double
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ret double %conv
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}
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; Test uitofp
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define float @uitofp_sw_i1(i1 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sw_i1
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; CHECK: and w0, w0, #0x1
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; CHECK: ucvtf s0, w0
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%conv = uitofp i1 %a to float
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ret float %conv
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}
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; Test uitofp
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define float @uitofp_sw_i8(i8 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sw_i8
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; CHECK: uxtb w0, w0
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; CHECK: ucvtf s0, w0
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%conv = uitofp i8 %a to float
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ret float %conv
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}
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; Test uitofp
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define float @uitofp_sw_i16(i16 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sw_i16
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; CHECK: uxth w0, w0
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; CHECK: ucvtf s0, w0
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%conv = uitofp i16 %a to float
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ret float %conv
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}
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; Test uitofp
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define float @uitofp_sw(i32 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sw
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; CHECK: ucvtf s0, w0
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%conv = uitofp i32 %a to float
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ret float %conv
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}
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; Test uitofp
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define float @uitofp_sx(i64 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sx
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; CHECK: ucvtf s0, x0
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%conv = uitofp i64 %a to float
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ret float %conv
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}
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; Test uitofp
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define double @uitofp_dw(i32 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_dw
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; CHECK: ucvtf d0, w0
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%conv = uitofp i32 %a to double
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ret double %conv
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}
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; Test uitofp
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define double @uitofp_dx(i64 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_dx
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; CHECK: ucvtf d0, x0
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%conv = uitofp i64 %a to double
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ret double %conv
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}
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define i32 @i64_trunc_i32(i64 %a) nounwind ssp {
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entry:
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; CHECK: i64_trunc_i32
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; CHECK: mov x1, x0
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%conv = trunc i64 %a to i32
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ret i32 %conv
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}
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define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {
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entry:
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; CHECK: i64_trunc_i16
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xffff
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; CHECK: uxth w0, [[REG2]]
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%conv = trunc i64 %a to i16
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ret i16 %conv
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}
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define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {
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entry:
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; CHECK: i64_trunc_i8
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xff
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; CHECK: uxtb w0, [[REG2]]
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%conv = trunc i64 %a to i8
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ret i8 %conv
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}
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define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {
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entry:
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; CHECK: i64_trunc_i1
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0x1
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; CHECK: and w0, [[REG2]], #0x1
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%conv = trunc i64 %a to i1
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ret i1 %conv
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}
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; rdar://15101939
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define void @stack_trunc() nounwind {
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; CHECK: stack_trunc
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; CHECK: sub sp, sp, #16
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; CHECK: ldr [[REG:x[0-9]+]], [sp]
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; CHECK: mov x[[REG2:[0-9]+]], [[REG]]
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; CHECK: and [[REG3:w[0-9]+]], w[[REG2]], #0xff
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; CHECK: strb [[REG3]], [sp, #15]
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; CHECK: add sp, sp, #16
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%a = alloca i8, align 1
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%b = alloca i64, align 8
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%c = load i64* %b, align 8
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%d = trunc i64 %c to i8
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store i8 %d, i8* %a, align 1
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ret void
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}
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define zeroext i64 @zext_i8_i64(i8 zeroext %in) {
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; CHECK-LABEL: zext_i8_i64:
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; CHECK: mov x[[TMP:[0-9]+]], x0
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; CHECK: ubfx x0, x[[TMP]], #0, #8
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%big = zext i8 %in to i64
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ret i64 %big
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}
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define zeroext i64 @zext_i16_i64(i16 zeroext %in) {
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; CHECK-LABEL: zext_i16_i64:
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; CHECK: mov x[[TMP:[0-9]+]], x0
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; CHECK: ubfx x0, x[[TMP]], #0, #16
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%big = zext i16 %in to i64
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ret i64 %big
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}
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