mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-29 13:29:28 +00:00
29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
278 lines
7.7 KiB
LLVM
278 lines
7.7 KiB
LLVM
; RUN: llc -march=arm64 -mtriple=arm64-apple-ios < %s | FileCheck %s
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;
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; <rdar://problem/13820218>
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define signext i16 @extendedLeftShiftcharToshortBy4(i8 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedLeftShiftcharToshortBy4:
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; CHECK: add [[REG:w[0-9]+]], w0, #1
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; CHECK: sbfiz w0, [[REG]], #4, #8
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%inc = add i8 %a, 1
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%conv1 = sext i8 %inc to i32
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%shl = shl nsw i32 %conv1, 4
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%conv2 = trunc i32 %shl to i16
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ret i16 %conv2
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}
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define signext i16 @extendedRightShiftcharToshortBy4(i8 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedRightShiftcharToshortBy4:
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; CHECK: add [[REG:w[0-9]+]], w0, #1
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; CHECK: sbfx w0, [[REG]], #4, #4
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%inc = add i8 %a, 1
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%conv1 = sext i8 %inc to i32
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%shr4 = lshr i32 %conv1, 4
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%conv2 = trunc i32 %shr4 to i16
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ret i16 %conv2
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}
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define signext i16 @extendedLeftShiftcharToshortBy8(i8 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedLeftShiftcharToshortBy8:
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; CHECK: add [[REG:w[0-9]+]], w0, #1
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; CHECK: sbfiz w0, [[REG]], #8, #8
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%inc = add i8 %a, 1
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%conv1 = sext i8 %inc to i32
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%shl = shl nsw i32 %conv1, 8
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%conv2 = trunc i32 %shl to i16
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ret i16 %conv2
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}
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define signext i16 @extendedRightShiftcharToshortBy8(i8 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedRightShiftcharToshortBy8:
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; CHECK: add [[REG:w[0-9]+]], w0, #1
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; CHECK: sxtb [[REG]], [[REG]]
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; CHECK: asr w0, [[REG]], #8
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%inc = add i8 %a, 1
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%conv1 = sext i8 %inc to i32
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%shr4 = lshr i32 %conv1, 8
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%conv2 = trunc i32 %shr4 to i16
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ret i16 %conv2
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}
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define i32 @extendedLeftShiftcharTointBy4(i8 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedLeftShiftcharTointBy4:
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; CHECK: add [[REG:w[0-9]+]], w0, #1
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; CHECK: sbfiz w0, [[REG]], #4, #8
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%inc = add i8 %a, 1
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%conv = sext i8 %inc to i32
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%shl = shl nsw i32 %conv, 4
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ret i32 %shl
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}
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define i32 @extendedRightShiftcharTointBy4(i8 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedRightShiftcharTointBy4:
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; CHECK: add [[REG:w[0-9]+]], w0, #1
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; CHECK: sbfx w0, [[REG]], #4, #4
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%inc = add i8 %a, 1
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%conv = sext i8 %inc to i32
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%shr = ashr i32 %conv, 4
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ret i32 %shr
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}
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define i32 @extendedLeftShiftcharTointBy8(i8 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedLeftShiftcharTointBy8:
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; CHECK: add [[REG:w[0-9]+]], w0, #1
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; CHECK: sbfiz w0, [[REG]], #8, #8
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%inc = add i8 %a, 1
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%conv = sext i8 %inc to i32
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%shl = shl nsw i32 %conv, 8
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ret i32 %shl
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}
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define i32 @extendedRightShiftcharTointBy8(i8 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedRightShiftcharTointBy8:
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; CHECK: add [[REG:w[0-9]+]], w0, #1
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; CHECK: sxtb [[REG]], [[REG]]
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; CHECK: asr w0, [[REG]], #8
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%inc = add i8 %a, 1
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%conv = sext i8 %inc to i32
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%shr = ashr i32 %conv, 8
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ret i32 %shr
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}
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define i64 @extendedLeftShiftcharToint64By4(i8 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedLeftShiftcharToint64By4:
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; CHECK: add w[[REG:[0-9]+]], w0, #1
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; CHECK: sbfiz x0, x[[REG]], #4, #8
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%inc = add i8 %a, 1
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%conv = sext i8 %inc to i64
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%shl = shl nsw i64 %conv, 4
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ret i64 %shl
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}
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define i64 @extendedRightShiftcharToint64By4(i8 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedRightShiftcharToint64By4:
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; CHECK: add w[[REG:[0-9]+]], w0, #1
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; CHECK: sbfx x0, x[[REG]], #4, #4
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%inc = add i8 %a, 1
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%conv = sext i8 %inc to i64
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%shr = ashr i64 %conv, 4
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ret i64 %shr
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}
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define i64 @extendedLeftShiftcharToint64By8(i8 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedLeftShiftcharToint64By8:
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; CHECK: add w[[REG:[0-9]+]], w0, #1
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; CHECK: sbfiz x0, x[[REG]], #8, #8
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%inc = add i8 %a, 1
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%conv = sext i8 %inc to i64
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%shl = shl nsw i64 %conv, 8
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ret i64 %shl
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}
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define i64 @extendedRightShiftcharToint64By8(i8 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedRightShiftcharToint64By8:
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; CHECK: add w[[REG:[0-9]+]], w0, #1
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; CHECK: sxtb x[[REG]], w[[REG]]
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; CHECK: asr x0, x[[REG]], #8
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%inc = add i8 %a, 1
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%conv = sext i8 %inc to i64
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%shr = ashr i64 %conv, 8
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ret i64 %shr
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}
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define i32 @extendedLeftShiftshortTointBy4(i16 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedLeftShiftshortTointBy4:
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; CHECK: add [[REG:w[0-9]+]], w0, #1
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; CHECK: sbfiz w0, [[REG]], #4, #16
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%inc = add i16 %a, 1
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%conv = sext i16 %inc to i32
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%shl = shl nsw i32 %conv, 4
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ret i32 %shl
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}
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define i32 @extendedRightShiftshortTointBy4(i16 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedRightShiftshortTointBy4:
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; CHECK: add [[REG:w[0-9]+]], w0, #1
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; CHECK: sbfx w0, [[REG]], #4, #12
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%inc = add i16 %a, 1
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%conv = sext i16 %inc to i32
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%shr = ashr i32 %conv, 4
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ret i32 %shr
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}
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define i32 @extendedLeftShiftshortTointBy16(i16 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedLeftShiftshortTointBy16:
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; CHECK: add [[REG:w[0-9]+]], w0, #1
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; CHECK: lsl w0, [[REG]], #16
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%inc = add i16 %a, 1
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%conv2 = zext i16 %inc to i32
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%shl = shl nuw i32 %conv2, 16
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ret i32 %shl
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}
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define i32 @extendedRightShiftshortTointBy16(i16 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedRightShiftshortTointBy16:
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; CHECK: add [[REG:w[0-9]+]], w0, #1
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; CHECK: sxth [[REG]], [[REG]]
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; CHECK: asr w0, [[REG]], #16
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%inc = add i16 %a, 1
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%conv = sext i16 %inc to i32
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%shr = ashr i32 %conv, 16
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ret i32 %shr
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}
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define i64 @extendedLeftShiftshortToint64By4(i16 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedLeftShiftshortToint64By4:
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; CHECK: add w[[REG:[0-9]+]], w0, #1
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; CHECK: sbfiz x0, x[[REG]], #4, #16
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%inc = add i16 %a, 1
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%conv = sext i16 %inc to i64
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%shl = shl nsw i64 %conv, 4
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ret i64 %shl
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}
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define i64 @extendedRightShiftshortToint64By4(i16 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedRightShiftshortToint64By4:
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; CHECK: add w[[REG:[0-9]+]], w0, #1
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; CHECK: sbfx x0, x[[REG]], #4, #12
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%inc = add i16 %a, 1
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%conv = sext i16 %inc to i64
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%shr = ashr i64 %conv, 4
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ret i64 %shr
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}
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define i64 @extendedLeftShiftshortToint64By16(i16 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedLeftShiftshortToint64By16:
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; CHECK: add w[[REG:[0-9]+]], w0, #1
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; CHECK: sbfiz x0, x[[REG]], #16, #16
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%inc = add i16 %a, 1
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%conv = sext i16 %inc to i64
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%shl = shl nsw i64 %conv, 16
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ret i64 %shl
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}
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define i64 @extendedRightShiftshortToint64By16(i16 signext %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedRightShiftshortToint64By16:
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; CHECK: add w[[REG:[0-9]+]], w0, #1
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; CHECK: sxth x[[REG]], w[[REG]]
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; CHECK: asr x0, x[[REG]], #16
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%inc = add i16 %a, 1
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%conv = sext i16 %inc to i64
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%shr = ashr i64 %conv, 16
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ret i64 %shr
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}
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define i64 @extendedLeftShiftintToint64By4(i32 %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedLeftShiftintToint64By4:
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; CHECK: add w[[REG:[0-9]+]], w0, #1
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; CHECK: sbfiz x0, x[[REG]], #4, #32
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%inc = add nsw i32 %a, 1
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%conv = sext i32 %inc to i64
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%shl = shl nsw i64 %conv, 4
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ret i64 %shl
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}
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define i64 @extendedRightShiftintToint64By4(i32 %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedRightShiftintToint64By4:
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; CHECK: add w[[REG:[0-9]+]], w0, #1
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; CHECK: sbfx x0, x[[REG]], #4, #28
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%inc = add nsw i32 %a, 1
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%conv = sext i32 %inc to i64
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%shr = ashr i64 %conv, 4
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ret i64 %shr
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}
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define i64 @extendedLeftShiftintToint64By32(i32 %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedLeftShiftintToint64By32:
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; CHECK: add w[[REG:[0-9]+]], w0, #1
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; CHECK: lsl x0, x[[REG]], #32
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%inc = add nsw i32 %a, 1
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%conv2 = zext i32 %inc to i64
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%shl = shl nuw i64 %conv2, 32
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ret i64 %shl
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}
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define i64 @extendedRightShiftintToint64By32(i32 %a) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: extendedRightShiftintToint64By32:
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; CHECK: add w[[REG:[0-9]+]], w0, #1
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; CHECK: sxtw x[[REG]], w[[REG]]
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; CHECK: asr x0, x[[REG]], #32
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%inc = add nsw i32 %a, 1
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%conv = sext i32 %inc to i64
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%shr = ashr i64 %conv, 32
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ret i64 %shr
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}
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