mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-25 14:30:32 +00:00
9105f66d6f
I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209576 91177308-0d34-0410-b5e6-96231b3b80d8
164 lines
4.4 KiB
LLVM
164 lines
4.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
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define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {
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; CHECK-LABEL: test_madd32:
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%mid = mul i32 %val1, %val2
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%res = add i32 %val0, %mid
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; CHECK: madd {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i32 %res
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}
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define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) {
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; CHECK-LABEL: test_madd64:
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%mid = mul i64 %val1, %val2
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%res = add i64 %val0, %mid
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; CHECK: madd {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) {
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; CHECK-LABEL: test_msub32:
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%mid = mul i32 %val1, %val2
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%res = sub i32 %val0, %mid
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; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i32 %res
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}
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define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) {
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; CHECK-LABEL: test_msub64:
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%mid = mul i64 %val1, %val2
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%res = sub i64 %val0, %mid
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; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) {
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; CHECK-LABEL: test_smaddl:
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%ext1 = sext i32 %val1 to i64
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%ext2 = sext i32 %val2 to i64
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%prod = mul i64 %ext1, %ext2
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%res = add i64 %acc, %prod
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; CHECK: smaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) {
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; CHECK-LABEL: test_smsubl:
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%ext1 = sext i32 %val1 to i64
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%ext2 = sext i32 %val2 to i64
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%prod = mul i64 %ext1, %ext2
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%res = sub i64 %acc, %prod
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; CHECK: smsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) {
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; CHECK-LABEL: test_umaddl:
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%ext1 = zext i32 %val1 to i64
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%ext2 = zext i32 %val2 to i64
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%prod = mul i64 %ext1, %ext2
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%res = add i64 %acc, %prod
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; CHECK: umaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) {
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; CHECK-LABEL: test_umsubl:
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%ext1 = zext i32 %val1 to i64
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%ext2 = zext i32 %val2 to i64
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%prod = mul i64 %ext1, %ext2
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%res = sub i64 %acc, %prod
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; CHECK: umsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i64 @test_smulh(i64 %lhs, i64 %rhs) {
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; CHECK-LABEL: test_smulh:
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%ext1 = sext i64 %lhs to i128
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%ext2 = sext i64 %rhs to i128
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%res = mul i128 %ext1, %ext2
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%high = lshr i128 %res, 64
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%val = trunc i128 %high to i64
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; CHECK: smulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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ret i64 %val
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}
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define i64 @test_umulh(i64 %lhs, i64 %rhs) {
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; CHECK-LABEL: test_umulh:
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%ext1 = zext i64 %lhs to i128
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%ext2 = zext i64 %rhs to i128
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%res = mul i128 %ext1, %ext2
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%high = lshr i128 %res, 64
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%val = trunc i128 %high to i64
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; CHECK: umulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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ret i64 %val
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}
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define i32 @test_mul32(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: test_mul32:
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%res = mul i32 %lhs, %rhs
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; CHECK: mul {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i32 %res
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}
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define i64 @test_mul64(i64 %lhs, i64 %rhs) {
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; CHECK-LABEL: test_mul64:
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%res = mul i64 %lhs, %rhs
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; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i32 @test_mneg32(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: test_mneg32:
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%prod = mul i32 %lhs, %rhs
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%res = sub i32 0, %prod
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; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i32 %res
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}
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define i64 @test_mneg64(i64 %lhs, i64 %rhs) {
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; CHECK-LABEL: test_mneg64:
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%prod = mul i64 %lhs, %rhs
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%res = sub i64 0, %prod
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; CHECK: mneg {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i64 @test_smull(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: test_smull:
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%ext1 = sext i32 %lhs to i64
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%ext2 = sext i32 %rhs to i64
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%res = mul i64 %ext1, %ext2
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; CHECK: smull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i64 %res
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}
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define i64 @test_umull(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: test_umull:
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%ext1 = zext i32 %lhs to i64
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%ext2 = zext i32 %rhs to i64
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%res = mul i64 %ext1, %ext2
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; CHECK: umull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i64 %res
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}
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define i64 @test_smnegl(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: test_smnegl:
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%ext1 = sext i32 %lhs to i64
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%ext2 = sext i32 %rhs to i64
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%prod = mul i64 %ext1, %ext2
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%res = sub i64 0, %prod
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; CHECK: smnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i64 %res
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}
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define i64 @test_umnegl(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: test_umnegl:
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%ext1 = zext i32 %lhs to i64
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%ext2 = zext i32 %rhs to i64
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%prod = mul i64 %ext1, %ext2
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%res = sub i64 0, %prod
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; CHECK: umnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i64 %res
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}
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