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Memory barrier __builtin_arm_[dmb, dsb, isb] intrinsics are required to implement their corresponding ACLE and MSVC intrinsics. This patch ports ARM dmb, dsb, isb intrinsic to AArch64. Differential Revision: http://reviews.llvm.org/D4520 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213247 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.6 KiB
LLVM
58 lines
1.6 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-eabi -O=3 | FileCheck %s
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define void @test() {
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; CHECK: dmb sy
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call void @llvm.aarch64.dmb(i32 15)
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; CHECK: dmb osh
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call void @llvm.aarch64.dmb(i32 3)
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; CHECK: dsb sy
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call void @llvm.aarch64.dsb(i32 15)
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; CHECK: dsb ishld
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call void @llvm.aarch64.dsb(i32 9)
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; CHECK: isb
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call void @llvm.aarch64.isb(i32 15)
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ret void
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}
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; Important point is that the compiler should not reorder memory access
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; instructions around DMB.
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; Failure to do so, two STRs will collapse into one STP.
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define void @test_dmb_reordering(i32 %a, i32 %b, i32* %d) {
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store i32 %a, i32* %d ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}]
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call void @llvm.aarch64.dmb(i32 15); CHECK: dmb sy
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%d1 = getelementptr i32* %d, i64 1
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store i32 %b, i32* %d1 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4]
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ret void
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}
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; Similarly for DSB.
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define void @test_dsb_reordering(i32 %a, i32 %b, i32* %d) {
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store i32 %a, i32* %d ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}]
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call void @llvm.aarch64.dsb(i32 15); CHECK: dsb sy
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%d1 = getelementptr i32* %d, i64 1
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store i32 %b, i32* %d1 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4]
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ret void
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}
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; And ISB.
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define void @test_isb_reordering(i32 %a, i32 %b, i32* %d) {
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store i32 %a, i32* %d ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}]
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call void @llvm.aarch64.isb(i32 15); CHECK: isb
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%d1 = getelementptr i32* %d, i64 1
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store i32 %b, i32* %d1 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4]
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ret void
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}
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declare void @llvm.aarch64.dmb(i32)
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declare void @llvm.aarch64.dsb(i32)
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declare void @llvm.aarch64.isb(i32)
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