mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-21 16:31:16 +00:00
897268d931
Summary: The immediate in these instructions is scaled before use as an offset. They therefore have a wider reach than ld.b/st.b. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D2338 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196775 91177308-0d34-0410-b5e6-96231b3b80d8
335 lines
10 KiB
LLVM
335 lines
10 KiB
LLVM
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-BE %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-LE %s
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define void @loadstore_v16i8_near() nounwind {
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; MIPS32-AE: loadstore_v16i8_near:
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%1 = alloca <16 x i8>
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%2 = load volatile <16 x i8>* %1
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; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0($sp)
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store volatile <16 x i8> %2, <16 x i8>* %1
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; MIPS32-AE: st.b [[R1]], 0($sp)
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ret void
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; MIPS32-AE: .size loadstore_v16i8_near
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}
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define void @loadstore_v16i8_just_under_simm10() nounwind {
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; MIPS32-AE: loadstore_v16i8_just_under_simm10:
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%1 = alloca <16 x i8>
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%2 = alloca [496 x i8] ; Push the frame right up to 512 bytes
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%3 = load volatile <16 x i8>* %1
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; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 496($sp)
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store volatile <16 x i8> %3, <16 x i8>* %1
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; MIPS32-AE: st.b [[R1]], 496($sp)
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ret void
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; MIPS32-AE: .size loadstore_v16i8_just_under_simm10
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}
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define void @loadstore_v16i8_just_over_simm10() nounwind {
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; MIPS32-AE: loadstore_v16i8_just_over_simm10:
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%1 = alloca <16 x i8>
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%2 = alloca [497 x i8] ; Push the frame just over 512 bytes
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%3 = load volatile <16 x i8>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 512
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; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <16 x i8> %3, <16 x i8>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 512
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; MIPS32-AE: st.b [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v16i8_just_over_simm10
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}
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define void @loadstore_v16i8_just_under_simm16() nounwind {
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; MIPS32-AE: loadstore_v16i8_just_under_simm16:
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%1 = alloca <16 x i8>
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%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
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%3 = load volatile <16 x i8>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <16 x i8> %3, <16 x i8>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.b [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v16i8_just_under_simm16
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}
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define void @loadstore_v16i8_just_over_simm16() nounwind {
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; MIPS32-AE: loadstore_v16i8_just_over_simm16:
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%1 = alloca <16 x i8>
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%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
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%3 = load volatile <16 x i8>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <16 x i8> %3, <16 x i8>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.b [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v16i8_just_over_simm16
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}
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define void @loadstore_v8i16_near() nounwind {
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; MIPS32-AE: loadstore_v8i16_near:
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%1 = alloca <8 x i16>
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%2 = load volatile <8 x i16>* %1
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; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0($sp)
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store volatile <8 x i16> %2, <8 x i16>* %1
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; MIPS32-AE: st.h [[R1]], 0($sp)
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ret void
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; MIPS32-AE: .size loadstore_v8i16_near
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}
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define void @loadstore_v8i16_just_under_simm10() nounwind {
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; MIPS32-AE: loadstore_v8i16_just_under_simm10:
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%1 = alloca <8 x i16>
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%2 = alloca [1008 x i8] ; Push the frame right up to 1024 bytes
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%3 = load volatile <8 x i16>* %1
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; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 1008($sp)
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store volatile <8 x i16> %3, <8 x i16>* %1
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; MIPS32-AE: st.h [[R1]], 1008($sp)
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ret void
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; MIPS32-AE: .size loadstore_v8i16_just_under_simm10
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}
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define void @loadstore_v8i16_just_over_simm10() nounwind {
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; MIPS32-AE: loadstore_v8i16_just_over_simm10:
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%1 = alloca <8 x i16>
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%2 = alloca [1009 x i8] ; Push the frame just over 1024 bytes
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%3 = load volatile <8 x i16>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1024
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; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <8 x i16> %3, <8 x i16>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1024
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; MIPS32-AE: st.h [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v8i16_just_over_simm10
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}
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define void @loadstore_v8i16_just_under_simm16() nounwind {
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; MIPS32-AE: loadstore_v8i16_just_under_simm16:
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%1 = alloca <8 x i16>
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%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
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%3 = load volatile <8 x i16>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <8 x i16> %3, <8 x i16>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.h [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v8i16_just_under_simm16
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}
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define void @loadstore_v8i16_just_over_simm16() nounwind {
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; MIPS32-AE: loadstore_v8i16_just_over_simm16:
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%1 = alloca <8 x i16>
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%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
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%3 = load volatile <8 x i16>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <8 x i16> %3, <8 x i16>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.h [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v8i16_just_over_simm16
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}
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define void @loadstore_v4i32_near() nounwind {
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; MIPS32-AE: loadstore_v4i32_near:
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%1 = alloca <4 x i32>
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%2 = load volatile <4 x i32>* %1
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; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0($sp)
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store volatile <4 x i32> %2, <4 x i32>* %1
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; MIPS32-AE: st.w [[R1]], 0($sp)
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ret void
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; MIPS32-AE: .size loadstore_v4i32_near
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}
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define void @loadstore_v4i32_just_under_simm10() nounwind {
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; MIPS32-AE: loadstore_v4i32_just_under_simm10:
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%1 = alloca <4 x i32>
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%2 = alloca [2032 x i8] ; Push the frame right up to 2048 bytes
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%3 = load volatile <4 x i32>* %1
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; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 2032($sp)
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store volatile <4 x i32> %3, <4 x i32>* %1
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; MIPS32-AE: st.w [[R1]], 2032($sp)
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ret void
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; MIPS32-AE: .size loadstore_v4i32_just_under_simm10
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}
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define void @loadstore_v4i32_just_over_simm10() nounwind {
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; MIPS32-AE: loadstore_v4i32_just_over_simm10:
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%1 = alloca <4 x i32>
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%2 = alloca [2033 x i8] ; Push the frame just over 2048 bytes
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%3 = load volatile <4 x i32>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 2048
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; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <4 x i32> %3, <4 x i32>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 2048
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; MIPS32-AE: st.w [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v4i32_just_over_simm10
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}
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define void @loadstore_v4i32_just_under_simm16() nounwind {
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; MIPS32-AE: loadstore_v4i32_just_under_simm16:
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%1 = alloca <4 x i32>
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%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
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%3 = load volatile <4 x i32>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <4 x i32> %3, <4 x i32>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.w [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v4i32_just_under_simm16
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}
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define void @loadstore_v4i32_just_over_simm16() nounwind {
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; MIPS32-AE: loadstore_v4i32_just_over_simm16:
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%1 = alloca <4 x i32>
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%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
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%3 = load volatile <4 x i32>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <4 x i32> %3, <4 x i32>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.w [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v4i32_just_over_simm16
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}
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define void @loadstore_v2i64_near() nounwind {
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; MIPS32-AE: loadstore_v2i64_near:
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%1 = alloca <2 x i64>
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%2 = load volatile <2 x i64>* %1
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; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0($sp)
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store volatile <2 x i64> %2, <2 x i64>* %1
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; MIPS32-AE: st.d [[R1]], 0($sp)
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ret void
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; MIPS32-AE: .size loadstore_v2i64_near
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}
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define void @loadstore_v2i64_just_under_simm10() nounwind {
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; MIPS32-AE: loadstore_v2i64_just_under_simm10:
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%1 = alloca <2 x i64>
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%2 = alloca [4080 x i8] ; Push the frame right up to 4096 bytes
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%3 = load volatile <2 x i64>* %1
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; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 4080($sp)
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store volatile <2 x i64> %3, <2 x i64>* %1
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; MIPS32-AE: st.d [[R1]], 4080($sp)
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ret void
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; MIPS32-AE: .size loadstore_v2i64_just_under_simm10
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}
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define void @loadstore_v2i64_just_over_simm10() nounwind {
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; MIPS32-AE: loadstore_v2i64_just_over_simm10:
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%1 = alloca <2 x i64>
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%2 = alloca [4081 x i8] ; Push the frame just over 4096 bytes
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%3 = load volatile <2 x i64>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 4096
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; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <2 x i64> %3, <2 x i64>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 4096
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; MIPS32-AE: st.d [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v2i64_just_over_simm10
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}
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define void @loadstore_v2i64_just_under_simm16() nounwind {
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; MIPS32-AE: loadstore_v2i64_just_under_simm16:
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%1 = alloca <2 x i64>
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%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
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%3 = load volatile <2 x i64>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <2 x i64> %3, <2 x i64>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.d [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v2i64_just_under_simm16
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}
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define void @loadstore_v2i64_just_over_simm16() nounwind {
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; MIPS32-AE: loadstore_v2i64_just_over_simm16:
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%1 = alloca <2 x i64>
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%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
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%3 = load volatile <2 x i64>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <2 x i64> %3, <2 x i64>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.d [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v2i64_just_over_simm16
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}
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