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https://github.com/c64scene-ar/llvm-6502.git
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[mips][msa] Fix suboptimal FrameIndex lowering for ld.[hwd] and st.[hwd]
Summary: The immediate in these instructions is scaled before use as an offset. They therefore have a wider reach than ld.b/st.b. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D2338 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196775 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
84744f6916
commit
897268d931
@ -62,21 +62,25 @@ MipsSERegisterInfo::intRegClass(unsigned Size) const {
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return &Mips::GPR64RegClass;
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}
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/// Determine whether a given opcode is an MSA load/store (supporting 10-bit
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/// offsets) or a non-MSA load/store (supporting 16-bit offsets).
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static inline bool isMSALoadOrStore(const unsigned Opcode) {
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/// Get the size of the offset supported by the given load/store.
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/// The result includes the effects of any scale factors applied to the
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/// instruction immediate.
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static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) {
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switch (Opcode) {
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case Mips::LD_B:
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case Mips::LD_H:
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case Mips::LD_W:
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case Mips::LD_D:
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case Mips::ST_B:
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return 10;
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case Mips::LD_H:
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case Mips::ST_H:
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return 10 + 1 /* scale factor */;
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case Mips::LD_W:
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case Mips::ST_W:
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return 10 + 2 /* scale factor */;
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case Mips::LD_D:
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case Mips::ST_D:
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return true;
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return 10 + 3 /* scale factor */;
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default:
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return false;
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return 16;
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}
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}
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@ -131,13 +135,14 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
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if (!MI.isDebugValue()) {
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// Make sure Offset fits within the field available.
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// For MSA instructions, this is a 10-bit signed immediate, otherwise it is
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// a 16-bit signed immediate.
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unsigned OffsetBitSize = isMSALoadOrStore(MI.getOpcode()) ? 10 : 16;
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// For MSA instructions, this is a 10-bit signed immediate (scaled by
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// element size), otherwise it is a 16-bit signed immediate.
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unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode());
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if (OffsetBitSize == 10 && !isInt<10>(Offset) && isInt<16>(Offset)) {
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// If we have an offset that needs to fit into a signed 10-bit immediate
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// and doesn't, but does fit into 16-bits then use an ADDiu
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if (OffsetBitSize < 16 && !isIntN(OffsetBitSize, Offset) &&
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isInt<16>(Offset)) {
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// If we have an offset that needs to fit into a signed n-bit immediate
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// (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = II->getDebugLoc();
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unsigned ADDiu = Subtarget.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
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@ -83,3 +83,252 @@ define void @loadstore_v16i8_just_over_simm16() nounwind {
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ret void
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; MIPS32-AE: .size loadstore_v16i8_just_over_simm16
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}
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define void @loadstore_v8i16_near() nounwind {
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; MIPS32-AE: loadstore_v8i16_near:
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%1 = alloca <8 x i16>
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%2 = load volatile <8 x i16>* %1
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; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0($sp)
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store volatile <8 x i16> %2, <8 x i16>* %1
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; MIPS32-AE: st.h [[R1]], 0($sp)
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ret void
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; MIPS32-AE: .size loadstore_v8i16_near
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}
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define void @loadstore_v8i16_just_under_simm10() nounwind {
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; MIPS32-AE: loadstore_v8i16_just_under_simm10:
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%1 = alloca <8 x i16>
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%2 = alloca [1008 x i8] ; Push the frame right up to 1024 bytes
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%3 = load volatile <8 x i16>* %1
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; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 1008($sp)
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store volatile <8 x i16> %3, <8 x i16>* %1
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; MIPS32-AE: st.h [[R1]], 1008($sp)
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ret void
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; MIPS32-AE: .size loadstore_v8i16_just_under_simm10
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}
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define void @loadstore_v8i16_just_over_simm10() nounwind {
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; MIPS32-AE: loadstore_v8i16_just_over_simm10:
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%1 = alloca <8 x i16>
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%2 = alloca [1009 x i8] ; Push the frame just over 1024 bytes
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%3 = load volatile <8 x i16>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1024
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; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <8 x i16> %3, <8 x i16>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1024
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; MIPS32-AE: st.h [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v8i16_just_over_simm10
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}
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define void @loadstore_v8i16_just_under_simm16() nounwind {
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; MIPS32-AE: loadstore_v8i16_just_under_simm16:
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%1 = alloca <8 x i16>
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%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
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%3 = load volatile <8 x i16>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <8 x i16> %3, <8 x i16>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.h [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v8i16_just_under_simm16
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}
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define void @loadstore_v8i16_just_over_simm16() nounwind {
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; MIPS32-AE: loadstore_v8i16_just_over_simm16:
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%1 = alloca <8 x i16>
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%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
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%3 = load volatile <8 x i16>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <8 x i16> %3, <8 x i16>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.h [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v8i16_just_over_simm16
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}
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define void @loadstore_v4i32_near() nounwind {
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; MIPS32-AE: loadstore_v4i32_near:
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%1 = alloca <4 x i32>
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%2 = load volatile <4 x i32>* %1
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; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0($sp)
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store volatile <4 x i32> %2, <4 x i32>* %1
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; MIPS32-AE: st.w [[R1]], 0($sp)
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ret void
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; MIPS32-AE: .size loadstore_v4i32_near
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}
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define void @loadstore_v4i32_just_under_simm10() nounwind {
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; MIPS32-AE: loadstore_v4i32_just_under_simm10:
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%1 = alloca <4 x i32>
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%2 = alloca [2032 x i8] ; Push the frame right up to 2048 bytes
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%3 = load volatile <4 x i32>* %1
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; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 2032($sp)
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store volatile <4 x i32> %3, <4 x i32>* %1
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; MIPS32-AE: st.w [[R1]], 2032($sp)
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ret void
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; MIPS32-AE: .size loadstore_v4i32_just_under_simm10
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}
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define void @loadstore_v4i32_just_over_simm10() nounwind {
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; MIPS32-AE: loadstore_v4i32_just_over_simm10:
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%1 = alloca <4 x i32>
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%2 = alloca [2033 x i8] ; Push the frame just over 2048 bytes
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%3 = load volatile <4 x i32>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 2048
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; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <4 x i32> %3, <4 x i32>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 2048
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; MIPS32-AE: st.w [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v4i32_just_over_simm10
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}
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define void @loadstore_v4i32_just_under_simm16() nounwind {
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; MIPS32-AE: loadstore_v4i32_just_under_simm16:
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%1 = alloca <4 x i32>
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%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
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%3 = load volatile <4 x i32>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <4 x i32> %3, <4 x i32>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.w [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v4i32_just_under_simm16
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}
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define void @loadstore_v4i32_just_over_simm16() nounwind {
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; MIPS32-AE: loadstore_v4i32_just_over_simm16:
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%1 = alloca <4 x i32>
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%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
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%3 = load volatile <4 x i32>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <4 x i32> %3, <4 x i32>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.w [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v4i32_just_over_simm16
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}
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define void @loadstore_v2i64_near() nounwind {
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; MIPS32-AE: loadstore_v2i64_near:
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%1 = alloca <2 x i64>
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%2 = load volatile <2 x i64>* %1
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; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0($sp)
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store volatile <2 x i64> %2, <2 x i64>* %1
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; MIPS32-AE: st.d [[R1]], 0($sp)
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ret void
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; MIPS32-AE: .size loadstore_v2i64_near
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}
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define void @loadstore_v2i64_just_under_simm10() nounwind {
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; MIPS32-AE: loadstore_v2i64_just_under_simm10:
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%1 = alloca <2 x i64>
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%2 = alloca [4080 x i8] ; Push the frame right up to 4096 bytes
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%3 = load volatile <2 x i64>* %1
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; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 4080($sp)
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store volatile <2 x i64> %3, <2 x i64>* %1
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; MIPS32-AE: st.d [[R1]], 4080($sp)
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ret void
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; MIPS32-AE: .size loadstore_v2i64_just_under_simm10
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}
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define void @loadstore_v2i64_just_over_simm10() nounwind {
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; MIPS32-AE: loadstore_v2i64_just_over_simm10:
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%1 = alloca <2 x i64>
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%2 = alloca [4081 x i8] ; Push the frame just over 4096 bytes
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%3 = load volatile <2 x i64>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 4096
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; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <2 x i64> %3, <2 x i64>* %1
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; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 4096
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; MIPS32-AE: st.d [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v2i64_just_over_simm10
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}
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define void @loadstore_v2i64_just_under_simm16() nounwind {
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; MIPS32-AE: loadstore_v2i64_just_under_simm16:
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%1 = alloca <2 x i64>
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%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
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%3 = load volatile <2 x i64>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <2 x i64> %3, <2 x i64>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.d [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v2i64_just_under_simm16
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}
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define void @loadstore_v2i64_just_over_simm16() nounwind {
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; MIPS32-AE: loadstore_v2i64_just_over_simm16:
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%1 = alloca <2 x i64>
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%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
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%3 = load volatile <2 x i64>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
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store volatile <2 x i64> %3, <2 x i64>* %1
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; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
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; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
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; MIPS32-AE: st.d [[R1]], 0([[BASE]])
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ret void
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; MIPS32-AE: .size loadstore_v2i64_just_over_simm16
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}
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