Daniel Sanders fe6bd52bf2 [mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern. ... Summary: Correct the match patterns and the lowerings that made the CodeGen tests pass despite the mistakes. The original testcase that discovered the problem was SingleSource/UnitTests/SignlessType/factor.c in test-suite. During review, we also found that some of the existing CodeGen tests were incorrect and fixed them: * bitwise.ll: In bsel_v16i8 the IfSet/IfClear were reversed because bsel and bmnz have different operand orders and the test didn't correctly account for this. bmnz goes 'IfClear, IfSet, CondMask', while bsel goes 'CondMask, IfClear, IfSet'. * vec.ll: In the cases where a bsel is emitted as a bmnz (they are the same operation with a different input tied to the result) the operands were in the wrong order. * compare.ll and compare_float.ll: The bsel operand order was correct for a greater-than comparison, but a greater-than comparison instruction doesn't exist. Lowering this operation inverts the condition so the IfSet/IfClear need to be swapped to match. The differences between BSEL, BMNZ, and BMZ and how they map to/from vselect are rather confusing. I've therefore added a note to MSA.txt to explain this in a single place in addition to the comments that explain each case. Reviewers: matheusalmeida, jacksprat Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3028 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203657 91177308-0d34-0410-b5e6-96231b3b80d8		2014-03-12 11:54:00 +00:00
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AArch64	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
ARM	ARM: correct Dwarf output for non-contiguous VFP saves.	2014-03-12 11:29:23 +00:00
CPP	Begin adding docs and IR-level support for the inalloca attribute	2013-12-19 02:14:12 +00:00
Generic	CommandLine: Exit successfully for -version and -help	2014-02-28 19:08:01 +00:00
Hexagon	Fix broken CHECK lines	2014-02-16 07:31:05 +00:00
Inputs	Debug Info: update testing cases to specify the debug info version number.	2013-11-22 21:49:45 +00:00
Mips	[mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern.	2014-03-12 11:54:00 +00:00
MSP430	Fix known typos	2014-01-24 17:20:08 +00:00
NVPTX	Followup to r203483 - add test.	2014-03-10 20:36:04 +00:00
PowerPC	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
R600	R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCC	2014-03-07 20:12:39 +00:00
SPARC	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
SystemZ	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
Thumb	Add triples to try to fix the windows bots.	2014-02-13 16:49:47 +00:00
Thumb2	ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block	2014-02-26 11:27:28 +00:00
X86	X86: Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059)	2014-03-11 15:49:24 +00:00
XCore	[XCore] Add support for the "m" inline asm constraint.	2014-03-06 16:37:48 +00:00