Tim Northover 8af3f965e0 ARM: do not relax Thumb1 -> Thumb2 if only Thumb1 is available. ... After recognising that a certain narrow instruction might need a relocation to be represented, we used to unconditionally relax it to a Thumb2 instruction to permit this. Unfortunately, some CPUs (e.g. v6m) don't even have most Thumb2 instructions, so we end up emitting a completely invalid instruction. Theoretically, ELF does have relocations for these situations; but they are fairly unusable with such short ranges and the ABI document even says they're documented "for completeness". So an error is probably better there too. rdar://20391953 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234195 91177308-0d34-0410-b5e6-96231b3b80d8		2015-04-06 18:44:42 +00:00
..
AArch64	[AArch64] Add v8.1a "Rounding Double Multiply Add/Subtract" extension	2015-03-31 13:15:48 +00:00
ARM	ARM: do not relax Thumb1 -> Thumb2 if only Thumb1 is available.	2015-04-06 18:44:42 +00:00
AsmParser	Add support for .ifnes psuedo-op.	2015-03-18 14:20:54 +00:00
COFF	[opaque pointer type] Add textual IR support for explicit type parameter to gep operator	2015-03-13 18:20:45 +00:00
Disassembler	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
ELF	Use a comma after the unique keyword.	2015-04-06 16:34:41 +00:00
Hexagon	Expand MUX instructions early on Hexagon	2015-03-31 13:35:12 +00:00
MachO	MC: For variable symbols, maintain MCSymbol::Section as a cache.	2015-04-03 01:46:11 +00:00
Markup
Mips	[mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.	2015-03-17 13:17:44 +00:00
PowerPC	[PowerPC] Add asm parser support for bitmask forms of rotate-and-mask instructions	2015-03-28 19:42:41 +00:00
R600	R600/SI: Add a stub GCNTargetMachine	2015-01-06 18:00:21 +00:00
Sparc
SystemZ	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
X86	Fix the operand encoding in the test instruction.	2015-03-31 12:31:55 +00:00