Akira Hatanaka 44b6c715ac Add support for floating point base register + offset register addressing mode ... load and store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151611 91177308-0d34-0410-b5e6-96231b3b80d8		2012-02-28 02:55:02 +00:00
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Analysis	Duncan pointed out that if the alignment isn't explicitly specified, it defaults to the ABI alignment. Given that, make this code a bit more aggressive in such cases.	2012-02-27 23:16:46 +00:00
Archive
AsmParser
Bitcode
CodeGen	Handle regmasks in MachineCSE.	2012-02-28 02:08:50 +00:00
DebugInfo
ExecutionEngine	EE/Interpreter/ExternalFunctions.cpp: Staticize lle_X_() entries. They can be mapped in FuncNames[] at the initialization.	2012-02-24 00:20:08 +00:00
Linker	Add back removed code. It still causes LLVM to miscompile. But not having it breaks other things.	2012-02-27 23:48:30 +00:00
MC	ARM BL/BLX instruction fixups should use relocations.	2012-02-27 21:36:23 +00:00
Object	[Object] Add {begin,end}_dynamic_symbols stubs and implementation for ELF.	2012-02-28 00:40:37 +00:00
Support	Fix undefined behavior.	2012-02-24 19:06:15 +00:00
TableGen	Add Foreach Loop	2012-02-22 16:09:41 +00:00
Target	Add support for floating point base register + offset register addressing mode	2012-02-28 02:55:02 +00:00
Transforms	Plog a memleak in GlobalOpt.	2012-02-27 12:48:24 +00:00
VMCore	Use the DT dominates function in the verifier.	2012-02-26 02:23:37 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile