6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-29 10:32:47 +00:00
Code Issues Projects Releases Wiki Activity
8b6a26ca85
llvm-6502/test/CodeGen/AArch64/arm64-arith-saturating.ll
Tim Northover 29f94c7201 AArch64/ARM64: move ARM64 into AArch64's place 
This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.

"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.

This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 12:50:23 +00:00

154 lines
5.5 KiB
LLVM
Raw Blame History

; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
define i32 @qadds(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: qadds:
; CHECK: sqadd s0, s0, s1
%vecext = extractelement <4 x i32> %b, i32 0
%vecext1 = extractelement <4 x i32> %c, i32 0
%vqadd.i = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %vecext, i32 %vecext1) nounwind
ret i32 %vqadd.i
}
define i64 @qaddd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: qaddd:
; CHECK: sqadd d0, d0, d1
%vecext = extractelement <2 x i64> %b, i32 0
%vecext1 = extractelement <2 x i64> %c, i32 0
%vqadd.i = tail call i64 @llvm.aarch64.neon.sqadd.i64(i64 %vecext, i64 %vecext1) nounwind
ret i64 %vqadd.i
}
define i32 @uqadds(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: uqadds:
; CHECK: uqadd s0, s0, s1
%vecext = extractelement <4 x i32> %b, i32 0
%vecext1 = extractelement <4 x i32> %c, i32 0
%vqadd.i = tail call i32 @llvm.aarch64.neon.uqadd.i32(i32 %vecext, i32 %vecext1) nounwind
ret i32 %vqadd.i
}
define i64 @uqaddd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: uqaddd:
; CHECK: uqadd d0, d0, d1
%vecext = extractelement <2 x i64> %b, i32 0
%vecext1 = extractelement <2 x i64> %c, i32 0
%vqadd.i = tail call i64 @llvm.aarch64.neon.uqadd.i64(i64 %vecext, i64 %vecext1) nounwind
ret i64 %vqadd.i
}
declare i64 @llvm.aarch64.neon.uqadd.i64(i64, i64) nounwind readnone
declare i32 @llvm.aarch64.neon.uqadd.i32(i32, i32) nounwind readnone
declare i64 @llvm.aarch64.neon.sqadd.i64(i64, i64) nounwind readnone
declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32) nounwind readnone
define i32 @qsubs(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: qsubs:
; CHECK: sqsub s0, s0, s1
%vecext = extractelement <4 x i32> %b, i32 0
%vecext1 = extractelement <4 x i32> %c, i32 0
%vqsub.i = tail call i32 @llvm.aarch64.neon.sqsub.i32(i32 %vecext, i32 %vecext1) nounwind
ret i32 %vqsub.i
}
define i64 @qsubd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: qsubd:
; CHECK: sqsub d0, d0, d1
%vecext = extractelement <2 x i64> %b, i32 0
%vecext1 = extractelement <2 x i64> %c, i32 0
%vqsub.i = tail call i64 @llvm.aarch64.neon.sqsub.i64(i64 %vecext, i64 %vecext1) nounwind
ret i64 %vqsub.i
}
define i32 @uqsubs(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: uqsubs:
; CHECK: uqsub s0, s0, s1
%vecext = extractelement <4 x i32> %b, i32 0
%vecext1 = extractelement <4 x i32> %c, i32 0
%vqsub.i = tail call i32 @llvm.aarch64.neon.uqsub.i32(i32 %vecext, i32 %vecext1) nounwind
ret i32 %vqsub.i
}
define i64 @uqsubd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: uqsubd:
; CHECK: uqsub d0, d0, d1
%vecext = extractelement <2 x i64> %b, i32 0
%vecext1 = extractelement <2 x i64> %c, i32 0
%vqsub.i = tail call i64 @llvm.aarch64.neon.uqsub.i64(i64 %vecext, i64 %vecext1) nounwind
ret i64 %vqsub.i
}
declare i64 @llvm.aarch64.neon.uqsub.i64(i64, i64) nounwind readnone
declare i32 @llvm.aarch64.neon.uqsub.i32(i32, i32) nounwind readnone
declare i64 @llvm.aarch64.neon.sqsub.i64(i64, i64) nounwind readnone
declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32) nounwind readnone
define i32 @qabss(<4 x i32> %b, <4 x i32> %c) nounwind readnone {
; CHECK-LABEL: qabss:
; CHECK: sqabs s0, s0
; CHECK: ret
%vecext = extractelement <4 x i32> %b, i32 0
%vqabs.i = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %vecext) nounwind
ret i32 %vqabs.i
}
define i64 @qabsd(<2 x i64> %b, <2 x i64> %c) nounwind readnone {
; CHECK-LABEL: qabsd:
; CHECK: sqabs d0, d0
; CHECK: ret
%vecext = extractelement <2 x i64> %b, i32 0
%vqabs.i = tail call i64 @llvm.aarch64.neon.sqabs.i64(i64 %vecext) nounwind
ret i64 %vqabs.i
}
define i32 @qnegs(<4 x i32> %b, <4 x i32> %c) nounwind readnone {
; CHECK-LABEL: qnegs:
; CHECK: sqneg s0, s0
; CHECK: ret
%vecext = extractelement <4 x i32> %b, i32 0
%vqneg.i = tail call i32 @llvm.aarch64.neon.sqneg.i32(i32 %vecext) nounwind
ret i32 %vqneg.i
}
define i64 @qnegd(<2 x i64> %b, <2 x i64> %c) nounwind readnone {
; CHECK-LABEL: qnegd:
; CHECK: sqneg d0, d0
; CHECK: ret
%vecext = extractelement <2 x i64> %b, i32 0
%vqneg.i = tail call i64 @llvm.aarch64.neon.sqneg.i64(i64 %vecext) nounwind
ret i64 %vqneg.i
}
declare i64 @llvm.aarch64.neon.sqneg.i64(i64) nounwind readnone
declare i32 @llvm.aarch64.neon.sqneg.i32(i32) nounwind readnone
declare i64 @llvm.aarch64.neon.sqabs.i64(i64) nounwind readnone
declare i32 @llvm.aarch64.neon.sqabs.i32(i32) nounwind readnone
define i32 @vqmovund(<2 x i64> %b) nounwind readnone {
; CHECK-LABEL: vqmovund:
; CHECK: sqxtun s0, d0
%vecext = extractelement <2 x i64> %b, i32 0
%vqmovun.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtun.i32.i64(i64 %vecext) nounwind
ret i32 %vqmovun.i
}
define i32 @vqmovnd_s(<2 x i64> %b) nounwind readnone {
; CHECK-LABEL: vqmovnd_s:
; CHECK: sqxtn s0, d0
%vecext = extractelement <2 x i64> %b, i32 0
%vqmovn.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64 %vecext) nounwind
ret i32 %vqmovn.i
}
define i32 @vqmovnd_u(<2 x i64> %b) nounwind readnone {
; CHECK-LABEL: vqmovnd_u:
; CHECK: uqxtn s0, d0
%vecext = extractelement <2 x i64> %b, i32 0
%vqmovn.i = tail call i32 @llvm.aarch64.neon.scalar.uqxtn.i32.i64(i64 %vecext) nounwind
ret i32 %vqmovn.i
}
declare i32 @llvm.aarch64.neon.scalar.uqxtn.i32.i64(i64) nounwind readnone
declare i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64) nounwind readnone
declare i32 @llvm.aarch64.neon.scalar.sqxtun.i32.i64(i64) nounwind readnone
Reference in New Issue View Git Blame Copy Permalink